Show patches with: Submitter = Tamar Christina       |    State = Action Required       |   126 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[2/2,libsanitizer] hwasan: Remove testsuite check for a complaint message [PR112644] [1/2,libsanitizer] hwasan: Remove testsuite check for a complaint message [PR112644] - - - -1- 2024-01-31 Tamar Christina Unresolved
[1/2,libsanitizer] hwasan: Remove testsuite check for a complaint message [PR112644] [1/2,libsanitizer] hwasan: Remove testsuite check for a complaint message [PR112644] - - - -1- 2024-01-31 Tamar Christina Unresolved
[libsanitizer] : Sync fixes for asan interceptors from upstream [PR112644] [libsanitizer] : Sync fixes for asan interceptors from upstream [PR112644] - - - -1- 2024-01-29 Tamar Christina Unresolved
AArch64: Fix expansion of Advanced SIMD div and mul using SVE [PR109636] AArch64: Fix expansion of Advanced SIMD div and mul using SVE [PR109636] - - - -1- 2024-01-24 Tamar Christina Unresolved
[frontend] : don't ice with pragma NOVECTOR if loop in C has no condition [PR113267] [frontend] : don't ice with pragma NOVECTOR if loop in C has no condition [PR113267] - - - -1- 2024-01-08 Tamar Christina Unresolved
[20/21] Arm: Add Advanced SIMD cbranch implementation Untitled series #75645 - - - -1- 2023-12-29 Tamar Christina Unresolved
AArch64 Update costing for vector conversions [PR110625] AArch64 Update costing for vector conversions [PR110625] - - - -1- 2023-12-29 Tamar Christina Unresolved
[testsuite] : Add more pragma novector to new tests [testsuite] : Add more pragma novector to new tests - - - -1- 2023-12-24 Tamar Christina Unresolved
middle-end: Fix peeled vect loop IV values. middle-end: Fix peeled vect loop IV values. - - - -1- 2023-12-06 Tamar Christina Unresolved
middle-end: correct loop bounds for early breaks and peeled vector loops middle-end: correct loop bounds for early breaks and peeled vector loops - - - -1- 2023-12-06 Tamar Christina Unresolved
middle-end: refactor vectorizable_live_operation into helper method for codegen middle-end: refactor vectorizable_live_operation into helper method for codegen - - - -1- 2023-11-27 Tamar Christina Unresolved
middle-end: prevent LIM from hoising vector compares from gconds if target does not support it. middle-end: prevent LIM from hoising vector compares from gconds if target does not support it. - - - -1- 2023-11-27 Tamar Christina Unresolved
[6/6] AArch64: only emit mismatch error when features would be disabled. Untitled series #68489 - - - -1- 2023-11-15 Tamar Christina Unresolved
[2/6] AArch64: Remove special handling of generic cpu. Untitled series #68489 - - - -1- 2023-11-15 Tamar Christina Unresolved
AArch64: only discount MLA for vector and scalar statements AArch64: only discount MLA for vector and scalar statements - - - -1- 2023-11-15 Tamar Christina Unresolved
[v3,2/2] middle-end match.pd: optimize fneg (fabs (x)) to copysign (x, -1) [PR109154] [v3,1/2] middle-end: expand copysign handling from lockstep to nested iters - - - -1- 2023-11-06 Tamar Christina Unresolved
[v3,1/2] middle-end: expand copysign handling from lockstep to nested iters [v3,1/2] middle-end: expand copysign handling from lockstep to nested iters - - - -1- 2023-11-06 Tamar Christina Unresolved
[19/21] AArch64: Add optimization for vector cbranch combining SVE and Advanced SIMD Untitled series #67050 - - - -1- 2023-11-06 Tamar Christina Unresolved
[18/21] AArch64: Add optimization for vector != cbranch fed into compare with 0 for Advanced SIMD Untitled series #67039 - - - -1- 2023-11-06 Tamar Christina Unresolved
[17/21] AArch64: Add implementation for vector cbranch for Advanced SIMD Untitled series #67051 - - - -1- 2023-11-06 Tamar Christina Unresolved
[16/21] middle-end testsuite: un-xfail TSVC loops that check for exit control flow vectorization Untitled series #67038 - - - -1- 2023-11-06 Tamar Christina Unresolved
[15/21] middle-end: [RFC] conditionally support forcing final edge for debugging Untitled series #67025 - - - -1- 2023-11-06 Tamar Christina Unresolved
[14/21] middle-end: Change loop analysis from looking at at number of BB to actual cfg Untitled series #67041 - - - -1- 2023-11-06 Tamar Christina Unresolved
[13/21] middle-end: Update loop form analysis to support early break Untitled series #67046 - - - -1- 2023-11-06 Tamar Christina Unresolved
[12/21] middle-end: Add remaining changes to peeling and vectorizer to support early breaks Untitled series #67045 - - - -1- 2023-11-06 Tamar Christina Unresolved
[10/21] middle-end: implement relevancy analysis support for control flow Untitled series #67024 - - - -1- 2023-11-06 Tamar Christina Unresolved
[8/21] middle-end: update vectorizable_live_reduction with support for multiple exits and different… Untitled series #67023 - - - -1- 2023-11-06 Tamar Christina Unresolved
[7/21] middle-end: update IV update code to support early breaks and arbitrary exits Untitled series #67022 - - - -1- 2023-11-06 Tamar Christina Unresolved
[6/21] middle-end: support multiple exits in loop versioning Untitled series #67021 - - - -1- 2023-11-06 Tamar Christina Unresolved
[2/21] middle-end testsuite: Add tests for early break vectorization Untitled series #67020 - - - -1- 2023-11-06 Tamar Christina Unresolved
[1/21] middle-end testsuite: Add more pragma novector to new tests [1/21] middle-end testsuite: Add more pragma novector to new tests - - - -1- 2023-11-06 Tamar Christina Unresolved
middle-end: don't pass loop_vinfo to vect_set_loop_condition during prolog peeling [PR111866] middle-end: don't pass loop_vinfo to vect_set_loop_condition during prolog peeling [PR111866] - - - -1- 2023-10-20 Tamar Christina Unresolved
[5/6] AArch64: Fix Armv9-a warnings that get emitted whenever a ACLE header is used. Untitled series #62889 - - - -1- 2023-10-12 Tamar Christina Unresolved
AArch64 Add SVE implementation for cond_copysign. AArch64 Add SVE implementation for cond_copysign. - - - -1- 2023-10-05 Tamar Christina Unresolved
middle-end ifcvt: Add support for conditional copysign middle-end ifcvt: Add support for conditional copysign - - - -1- 2023-10-05 Tamar Christina Unresolved
AArch64 Handle copysign (x, -1) expansion efficiently AArch64 Handle copysign (x, -1) expansion efficiently - - - -1- 2023-10-05 Tamar Christina Unresolved
middle-end ifcvt: Allow any const IFN in conditional blocks middle-end ifcvt: Allow any const IFN in conditional blocks - - - -1- 2023-10-05 Tamar Christina Unresolved
middle-end: Recursively check is_trivially_copyable_or_pair in vec.h middle-end: Recursively check is_trivially_copyable_or_pair in vec.h - - - -1- 2023-10-02 Tamar Christina Unresolved
[3/3] middle-end: maintain LCSSA throughout loop peeling [1/3] middle-end: Refactor vectorizer loop conditionals and separate out IV to new variables - - - -1- 2023-10-02 Tamar Christina Unresolved
[2/3] middle-end: updated niters analysis to handle multiple exits. [1/3] middle-end: Refactor vectorizer loop conditionals and separate out IV to new variables - - - -1- 2023-10-02 Tamar Christina Unresolved
[1/3] middle-end: Refactor vectorizer loop conditionals and separate out IV to new variables [1/3] middle-end: Refactor vectorizer loop conditionals and separate out IV to new variables - - - -1- 2023-10-02 Tamar Christina Unresolved
AArch64 Rewrite simd move immediate patterns to new syntax AArch64 Rewrite simd move immediate patterns to new syntax - 1 - -1- 2023-09-27 Tamar Christina Unresolved
AArch64 Add special patterns for creating DI scalar and vector constant 1 << 63 [PR109154] AArch64 Add special patterns for creating DI scalar and vector constant 1 << 63 [PR109154] - - - -1- 2023-09-27 Tamar Christina Unresolved
AArch64: Use SVE unpredicated LOGICAL expressions when Advanced SIMD inefficient [PR109154] AArch64: Use SVE unpredicated LOGICAL expressions when Advanced SIMD inefficient [PR109154] - - - -1- 2023-09-27 Tamar Christina Unresolved
AArch64 Add movi for 0 moves for scalar types [PR109154] AArch64 Add movi for 0 moves for scalar types [PR109154] - - - -1- 2023-09-27 Tamar Christina Unresolved
middle-end match.pd: optimize fneg (fabs (x)) to x | (1 << signbit(x)) [PR109154] middle-end match.pd: optimize fneg (fabs (x)) to x | (1 << signbit(x)) [PR109154] - - - -1- 2023-09-27 Tamar Christina Unresolved
middle-end Fold vec_cond into conditional ternary or binary operation when sharing operand [PR10915… middle-end Fold vec_cond into conditional ternary or binary operation when sharing operand [PR10915… - - - -1- 2023-09-27 Tamar Christina Unresolved
middle-end ifcvt: replace C++ sort with vec::qsort [PR109154] middle-end ifcvt: replace C++ sort with vec::qsort [PR109154] - - - -1- 2023-09-19 Tamar Christina Unresolved
middle-end: relax validate_subreg to allow paradoxical subregs that change mode middle-end: relax validate_subreg to allow paradoxical subregs that change mode - - - -1- 2023-09-19 Tamar Christina Unresolved
AArch64 xorsign: Fix scalar xorsign lowering AArch64 xorsign: Fix scalar xorsign lowering - - - -1- 2023-09-01 Tamar Christina Unresolved
[gensupport] : Don't segfault on empty attrs list [gensupport] : Don't segfault on empty attrs list - - - -1- 2023-08-02 Tamar Christina Unresolved
AArch64 Undo vec_widen_<sur>shiftl optabs [PR106346] AArch64 Undo vec_widen_<sur>shiftl optabs [PR106346] - - - -1- 2023-08-02 Tamar Christina Unresolved
AArch64 update costing for combining vector conditionals AArch64 update costing for combining vector conditionals - - - -1- 2023-08-02 Tamar Christina Unresolved
AArch64 update costing for MLA by invariant AArch64 update costing for MLA by invariant - - - -1- 2023-08-02 Tamar Christina Unresolved
[2/2,frontend] : Add novector C pragma [1/2,frontend] Add novector C++ pragma - - - -1- 2023-07-19 Tamar Christina Unresolved
[1/2,frontend] Add novector C++ pragma [1/2,frontend] Add novector C++ pragma - - - -1- 2023-07-19 Tamar Christina Unresolved
AArch64 fix regexp for live_1.c sve test AArch64 fix regexp for live_1.c sve test - - - -1- 2023-07-18 Tamar Christina Unresolved
[2/2] middle-end ifcvt: Sort PHI arguments not only occurrences but also complexity [PR109154] [1/2] middle-end ifcvt: Reduce comparisons on conditionals by tracking truths [PR109154] - - - -1- 2023-07-07 Tamar Christina Unresolved
[1/2] middle-end ifcvt: Reduce comparisons on conditionals by tracking truths [PR109154] [1/2] middle-end ifcvt: Reduce comparisons on conditionals by tracking truths [PR109154] - - - -1- 2023-07-07 Tamar Christina Unresolved
[committed,docs] : replace backslashchar [PR 110329]. [committed,docs] : replace backslashchar [PR 110329]. - - - -1- 2023-06-21 Tamar Christina Unresolved
[gensupport] drop suppport for define_cond_exec from compact syntac [gensupport] drop suppport for define_cond_exec from compact syntac - - - -1- 2023-06-20 Tamar Christina Unresolved
[committed] AArch64 remove test comment from *mov<mode>_aarch64 [committed] AArch64 remove test comment from *mov<mode>_aarch64 - - - -1- 2023-06-20 Tamar Christina Unresolved
Remove DEFAULT_MATCHPD_PARTITIONS macro Remove DEFAULT_MATCHPD_PARTITIONS macro - - - -1- 2023-06-12 Tamar Christina Unresolved
[committed] Regenerate config.in [committed] Regenerate config.in - - - -1- 2023-06-12 Tamar Christina Unresolved
[5/5] match.pd: Use splits in makefile and make configurable. Untitled series #35893 - - - -1- 2023-04-28 Tamar Christina Unresolved
[3/5] genmatch: split shared code to gimple-match-exports.cc Untitled series #35893 - - - -1- 2023-04-28 Tamar Christina Unresolved
[3/5] match.pd: CSE the dump output check. Untitled series #35892 - - - -1- 2023-04-28 Tamar Christina Unresolved
[2/5] match.pd: Remove commented out line pragmas unless -vv is used. Untitled series #35892 - - - -1- 2023-04-28 Tamar Christina Unresolved
RFC: New compact syntax for insn and insn_split in Machine Descriptions RFC: New compact syntax for insn and insn_split in Machine Descriptions - - - -1- 2023-04-18 Tamar Christina Unresolved
[3/3] middle-end RFC - match.pd: automatically partition *-match.cc files. Untitled series #34182 - - - -1- 2023-04-18 Tamar Christina Unresolved
[2/3] middle-end match.pd: simplify debug dump checks Untitled series #34182 - - - -1- 2023-04-18 Tamar Christina Unresolved
[2/3] RFC - match.pd: simplify debug dump checks [1/3] RFC match.pd: don't emit label if not needed - - - -1- 2023-04-06 Tamar Christina Unresolved
[1/3] RFC match.pd: don't emit label if not needed [1/3] RFC match.pd: don't emit label if not needed - - - -1- 2023-04-06 Tamar Christina Unresolved
[3/3] RFC - match.pd: automatically partition *-match.cc files. [1/3] RFC match.pd: don't emit label if not needed - - - -1- 2023-04-06 Tamar Christina Unresolved
[committed,testsuite] : move mla_1 test to aarch64 only [PR109118] [committed,testsuite] : move mla_1 test to aarch64 only [PR109118] - - - -1- 2023-03-14 Tamar Christina Unresolved
middle-end: On emergency dumps finish the graph generation. middle-end: On emergency dumps finish the graph generation. - - - -1- 2023-03-07 Tamar Christina Unresolved
[4/4] AArch64 Update div-bitmask to implement new optab instead of target hook [PR108583] [1/4] middle-end: Revert can_special_div_by_const changes [PR108583] - - - -1- 2023-02-27 Tamar Christina Unresolved
[3/4] middle-end: Implement preferred_div_as_shifts_over_mult [PR108583] [1/4] middle-end: Revert can_special_div_by_const changes [PR108583] - - - -1- 2023-02-27 Tamar Christina Unresolved
[2/4,ranger] : Add range-ops for widen addition and widen multiplication [PR108583] [1/4] middle-end: Revert can_special_div_by_const changes [PR108583] - - - -1- 2023-02-27 Tamar Christina Unresolved
[1/4] middle-end: Revert can_special_div_by_const changes [PR108583] [1/4] middle-end: Revert can_special_div_by_const changes [PR108583] - - - -1- 2023-02-27 Tamar Christina Unresolved
[2/2] AArch64 Update div-bitmask to implement new optab instead of target hook [PR108583] [1/2] middle-end: Fix wrong overmatching of div-bitmask by using new optabs [PR108583] - - - -1- 2023-02-09 Tamar Christina Unresolved
[1/2] middle-end: Fix wrong overmatching of div-bitmask by using new optabs [PR108583] [1/2] middle-end: Fix wrong overmatching of div-bitmask by using new optabs [PR108583] - - - -1- 2023-02-09 Tamar Christina Unresolved
AArch64[committed] testsuite: remove broken test AArch64[committed] testsuite: remove broken test - - - -1- 2023-02-06 Tamar Christina Unresolved
AArch64: Fix codegen regressions around tbz. AArch64: Fix codegen regressions around tbz. - - - -1- 2023-01-27 Tamar Christina Unresolved
AArch64: Fix native detection in the presence of mandatory features which don't have midr values AArch64: Fix native detection in the presence of mandatory features which don't have midr values - - - -1- 2023-01-27 Tamar Christina Unresolved
AArch64 relax constraints on FP16 insn PR108172 AArch64 relax constraints on FP16 insn PR108172 - - - -1- 2022-12-20 Tamar Christina Unresolved
AArch64 Fix ILP32 tbranch AArch64 Fix ILP32 tbranch - - - -1- 2022-12-13 Tamar Christina Unresolved
AArch64 div-by-255, ensure that arguments are registers. [PR107988] AArch64 div-by-255, ensure that arguments are registers. [PR107988] - - - -1- 2022-12-08 Tamar Christina Unresolved
AArch64 sve2: Fix expansion of division [PR107830] AArch64 sve2: Fix expansion of division [PR107830] - - - -1- 2022-11-23 Tamar Christina Unresolved
middle-end: ensure that VEC_PERM operands get lowered to the same SSA_NAME. [PR107717] middle-end: ensure that VEC_PERM operands get lowered to the same SSA_NAME. [PR107717] - - - -1- 2022-11-17 Tamar Christina Unresolved
middle-end: replace GET_MODE_WIDER_MODE with GET_MODE_NEXT_MODE middle-end: replace GET_MODE_WIDER_MODE with GET_MODE_NEXT_MODE - - - -1- 2022-11-15 Tamar Christina Unresolved
[committed] middle-end: Fix addsub patch removing return statements [committed] middle-end: Fix addsub patch removing return statements - - - -1- 2022-11-14 Tamar Christina Unresolved
[committed] middle-end: Fix can_special_div_by_const doc. [committed] middle-end: Fix can_special_div_by_const doc. - - - -1- 2022-11-14 Tamar Christina Unresolved
AArch64 Fix vector re-interpretation between partial SIMD modes AArch64 Fix vector re-interpretation between partial SIMD modes - - - -1- 2022-11-11 Tamar Christina Unresolved
[i386] : Update ix86_can_change_mode_class target hook to accept QImode conversions [i386] : Update ix86_can_change_mode_class target hook to accept QImode conversions - - - -1- 2022-11-11 Tamar Christina Unresolved
[2/2] AArch64 Add implementation for vector cbranch. [1/2] middle-end: Support early break/return auto-vectorization. - - - -1- 2022-11-02 Tamar Christina Unresolved
[1/2] middle-end: Support early break/return auto-vectorization. [1/2] middle-end: Support early break/return auto-vectorization. - - - -1- 2022-11-02 Tamar Christina Unresolved
[8/8] AArch64: Have reload not choose to do add on the scalar side if both values exist on the SIMD… [1/8] middle-end: Recognize scalar reductions from bitfields and array_refs - - - -1- 2022-10-31 Tamar Christina Unresolved
[7/8] AArch64: Consolidate zero and sign extension patterns and add missing ones. [1/8] middle-end: Recognize scalar reductions from bitfields and array_refs - - - -1- 2022-10-31 Tamar Christina Unresolved
[6/8] AArch64: Add peephole and scheduling logic for pairwise operations that appear late in RTL. [1/8] middle-end: Recognize scalar reductions from bitfields and array_refs - - - -1- 2022-10-31 Tamar Christina Unresolved
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