Show patches with: Submitter = juzhe.zhong@rivai.ai       |    State = Action Required       |   652 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
RISC-V: Add unary C/C++ API support RISC-V: Add unary C/C++ API support - - - -1- 2023-02-03 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add binary vx C/C++ support RISC-V: Add binary vx C/C++ support - - - -1- 2023-02-03 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix constraint bug for binary operation RISC-V: Fix constraint bug for binary operation - - - -1- 2023-02-01 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix testcases check. RISC-V: Fix testcases check. - - - -1- 2023-01-27 juzhe.zhong@rivai.ai Repeat Merge
RISC-V: Add vlse/vsse C/C++ API intrinsics support RISC-V: Add vlse/vsse C/C++ API intrinsics support - - - -1- 2023-01-20 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix pred_mov constraint for vle.v RISC-V: Fix pred_mov constraint for vle.v - - - -1- 2023-01-19 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add vlm/vsm C/C++ API intrinsics support RISC-V: Add vlm/vsm C/C++ API intrinsics support - - - -1- 2023-01-19 juzhe.zhong@rivai.ai Unresolved
RISC-V: Finalize testcases for final version VSETVL PASS. RISC-V: Finalize testcases for final version VSETVL PASS. - - - -1- 2023-01-18 juzhe.zhong@rivai.ai Unresolved
RISC-V: Finalize VSETVL PASS implementation RISC-V: Finalize VSETVL PASS implementation - - - -1- 2023-01-18 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix bug of before_p function RISC-V: Fix bug of before_p function - - - -1- 2023-01-18 juzhe.zhong@rivai.ai Unresolved
RISC-V: Change parse_insn into public for future use. RISC-V: Change parse_insn into public for future use. - - - -1- 2023-01-18 juzhe.zhong@rivai.ai Unresolved
RISC-V: Clang-format some annotations[NFC] RISC-V: Clang-format some annotations[NFC] - - - -1- 2023-01-18 juzhe.zhong@rivai.ai Unresolved
RISC-V: Remove DCE in VSETVL PASS RISC-V: Remove DCE in VSETVL PASS - - - -1- 2023-01-18 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix incorrect attributes of vsetvl instructions pattern RISC-V: Fix incorrect attributes of vsetvl instructions pattern - - - -1- 2023-01-18 juzhe.zhong@rivai.ai Unresolved
RISC-V: Adjust testcases for AVL=REG support RISC-V: Adjust testcases for AVL=REG support - - - -1- 2023-01-09 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix bugs of supporting AVL=REG (single-real-def) in VSETVL PASS RISC-V: Fix bugs of supporting AVL=REG (single-real-def) in VSETVL PASS - - - -1- 2023-01-09 juzhe.zhong@rivai.ai Unresolved
RISC-V: Remove dirty_pat since it is redundant RISC-V: Remove dirty_pat since it is redundant - - - -1- 2023-01-09 juzhe.zhong@rivai.ai Unresolved
RISC-V: Avoid redundant flow in backward fusion RISC-V: Avoid redundant flow in backward fusion - - - -1- 2023-01-09 juzhe.zhong@rivai.ai Unresolved
RISC-V: Avoid redundant flow in forward fusion RISC-V: Avoid redundant flow in forward fusion - - - -1- 2023-01-09 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support vle.v/vse.v intrinsics RISC-V: Support vle.v/vse.v intrinsics - - - -1- 2022-12-23 juzhe.zhong@rivai.ai Unresolved
RISC-V: Simplify ASM checks 2 RISC-V: Simplify ASM checks 2 - - - -1- 2022-12-19 juzhe.zhong@rivai.ai Unresolved
RISC-V: Simplify ASM checks. RISC-V: Simplify ASM checks. - - - -1- 2022-12-19 juzhe.zhong@rivai.ai Unresolved
RISC-V: Remove unit-stride store from ta attribute RISC-V: Remove unit-stride store from ta attribute - - - -1- 2022-12-14 juzhe.zhong@rivai.ai Unresolved
RISC-V: Remove unused redundant vector attributes RISC-V: Remove unused redundant vector attributes - - - -1- 2022-12-14 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix annotation RISC-V: Fix annotation - - - -1- 2022-12-14 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support VSETVL PASS for RVV support RISC-V: Support VSETVL PASS for RVV support - - - -1- 2022-12-14 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support VSETVL PASS for RVV support RISC-V: Support VSETVL PASS for RVV support - - - -1- 2022-12-14 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support VSETVL PASS for RVV support RISC-V: Support VSETVL PASS for RVV support - - - -1- 2022-12-14 juzhe.zhong@rivai.ai Unresolved
RISC-V: Remove tail && mask policy operand for vmclr, vmset, vmld, vmst RISC-V: Remove tail && mask policy operand for vmclr, vmset, vmld, vmst - - - -1- 2022-11-29 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add attributes for VSETVL PASS RISC-V: Add attributes for VSETVL PASS - - - -1- 2022-11-28 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add RVV registers register spilling RISC-V: Add RVV registers register spilling - - - -1- 2022-11-06 juzhe.zhong@rivai.ai Unresolved
RISC-V: ADJUST_NUNITS according to -march. RISC-V: ADJUST_NUNITS according to -march. - - - -1- 2022-10-25 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support (set (mem) (const_poly_int)) RISC-V: Support (set (mem) (const_poly_int)) - - - -1- 2022-10-24 juzhe.zhong@rivai.ai Unresolved
RISC-V: Replace CONSTEXPR with constexpr RISC-V: Replace CONSTEXPR with constexpr - - - -1- 2022-10-24 juzhe.zhong@rivai.ai Repeat Merge
RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests. RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests. - - - -1- 2022-10-17 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix format[NFC] RISC-V: Fix format[NFC] - - - -1- 2022-10-17 juzhe.zhong@rivai.ai Repeat Merge
RISC-V: Add new line at end of file. RISC-V: Add new line at end of file. - - - --- 2022-10-12 juzhe.zhong@rivai.ai New
RISC-V: Refine register_builtin_types function. RISC-V: Refine register_builtin_types function. - - - --- 2022-10-11 juzhe.zhong@rivai.ai New
RISC-V: Suppress riscv-selftests.cc warning. RISC-V: Suppress riscv-selftests.cc warning. - - - --- 2022-09-17 juzhe.zhong@rivai.ai New
RISC-V: Add RVV registers in TARGET_CONDITION_AL_REGISTER_USAGE RISC-V: Add RVV registers in TARGET_CONDITION_AL_REGISTER_USAGE - - - --- 2022-08-30 juzhe.zhong@rivai.ai New
RISC-V: Add csrr vlenb instruction. RISC-V: Add csrr vlenb instruction. - - - --- 2022-08-30 juzhe.zhong@rivai.ai New
RISC-V: Add RVV constraints. RISC-V: Add RVV constraints. - - - --- 2022-08-30 juzhe.zhong@rivai.ai New
RISC-V: Fix annotation RISC-V: Fix annotation - - - --- 2022-08-30 juzhe.zhong@rivai.ai New
RISC-V: Fix riscv_vector_chunks configuration according to TARGET_MIN_VLEN RISC-V: Fix riscv_vector_chunks configuration according to TARGET_MIN_VLEN - - - --- 2022-08-30 juzhe.zhong@rivai.ai New
RISC-V: Add RVV registers RISC-V: Add RVV registers - - - --- 2022-08-27 juzhe.zhong@rivai.ai New
RISC-V: Add RVV instructions classification RISC-V: Add RVV instructions classification - - - --- 2022-08-27 juzhe.zhong@rivai.ai New
RISC-V: Add vector registers and classification RISC-V: Add vector registers and classification - - - --- 2022-08-26 juzhe.zhong@rivai.ai New
middle-end: Fix unexpected warnings for RISC-V port. middle-end: Fix unexpected warnings for RISC-V port. - - - --- 2022-08-23 juzhe.zhong@rivai.ai New
middle-end: Fix issue of poly_uint16 (1, 1) in self test middle-end: Fix issue of poly_uint16 (1, 1) in self test - - - --- 2022-08-22 juzhe.zhong@rivai.ai New
middle-end: skipp stepped vector test of poly_int (1, 1) and allow the machine_mode definition with… middle-end: skipp stepped vector test of poly_int (1, 1) and allow the machine_mode definition with… - - - --- 2022-08-18 juzhe.zhong@rivai.ai New
RISC-V: Add runtime invariant support RISC-V: Add runtime invariant support - - - --- 2022-08-17 juzhe.zhong@rivai.ai New
[1/1] Fix bit-position comparison middle-end: Fix bit position comparison - - - --- 2022-07-27 juzhe.zhong@rivai.ai New
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