Show patches with: Submitter = juzhe.zhong@rivai.ai       |    State = Action Required       |   652 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
RISC-V: Remove redundant printf of abs-run.c RISC-V: Remove redundant printf of abs-run.c - - - -1- 2023-05-29 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Add RVV FMA auto-vectorization support [V2] RISC-V: Add RVV FMA auto-vectorization support - - - -1- 2023-05-26 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add RVV FMA auto-vectorization support RISC-V: Add RVV FMA auto-vectorization support - - - -1- 2023-05-26 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Fix zero-scratch-regs-3.c fail [V2] RISC-V: Fix zero-scratch-regs-3.c fail - - - -1- 2023-05-26 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix zero-scratch-regs-3.c fail RISC-V: Fix zero-scratch-regs-3.c fail - - - -1- 2023-05-25 juzhe.zhong@rivai.ai Unresolved
VECT: Add SELECT_VL support VECT: Add SELECT_VL support - - - -1- 2023-05-25 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add RVV FRM enum for floating-point rounding mode intriniscs RISC-V: Add RVV FRM enum for floating-point rounding mode intriniscs - - - -1- 2023-05-25 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Fix incorrect VXRM configuration in mode switching for CALL and ASM [V2] RISC-V: Fix incorrect VXRM configuration in mode switching for CALL and ASM - - - -1- 2023-05-25 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix incorrect VXRM configuration in mode switching for CALL and ASM RISC-V: Fix incorrect VXRM configuration in mode switching for CALL and ASM - - - -1- 2023-05-25 juzhe.zhong@rivai.ai Unresolved
RISC-V: Remove FRM_REGNUM dependency for rtx conversions RISC-V: Remove FRM_REGNUM dependency for rtx conversions - - - -1- 2023-05-24 juzhe.zhong@rivai.ai Repeat Merge
RISC-V: Add FRM_ prefix to dynamic rounding mode enum RISC-V: Add FRM_ prefix to dynamic rounding mode enum - - - -1- 2023-05-24 juzhe.zhong@rivai.ai Unresolved
[V2,COMMITTED] RISC-V: Add RVV mask logic auto-vectorization [V2,COMMITTED] RISC-V: Add RVV mask logic auto-vectorization - - - -1- 2023-05-24 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add RVV mask logic auto-vectorization RISC-V: Add RVV mask logic auto-vectorization - - - -1- 2023-05-24 juzhe.zhong@rivai.ai Unresolved
[V5] RISC-V: Add RVV comparison autovectorization [V5] RISC-V: Add RVV comparison autovectorization - - - -1- 2023-05-24 juzhe.zhong@rivai.ai Unresolved
[V4] RISC-V: Add RVV comparison autovectorization [V4] RISC-V: Add RVV comparison autovectorization - - - -1- 2023-05-24 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Fix incorrect code of reaching inaccessible memory address [V2] RISC-V: Fix incorrect code of reaching inaccessible memory address - - - -1- 2023-05-24 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix incorrect code of touching inaccessible memory address RISC-V: Fix incorrect code of touching inaccessible memory address - - - -1- 2023-05-24 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Fix magic number of RVV auto-vectorization expander [V2] RISC-V: Fix magic number of RVV auto-vectorization expander - 2 - -1- 2023-05-24 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix magic number of RVV auto-vectorization expander RISC-V: Fix magic number of RVV auto-vectorization expander - - - -1- 2023-05-24 juzhe.zhong@rivai.ai Unresolved
[V3] RISC-V: Add RVV comparison autovectorization [V3] RISC-V: Add RVV comparison autovectorization - - - -1- 2023-05-23 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Add RVV comparison autovectorization [V2] RISC-V: Add RVV comparison autovectorization - - - -1- 2023-05-23 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix warning of vxrm pattern RISC-V: Fix warning of vxrm pattern - - - -1- 2023-05-23 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Refactor the framework of RVV auto-vectorization [V2] RISC-V: Refactor the framework of RVV auto-vectorization - - - -1- 2023-05-23 juzhe.zhong@rivai.ai Unresolved
RISC-V: Refactor the framework of RVV auto-vectorization RISC-V: Refactor the framework of RVV auto-vectorization - - - -1- 2023-05-23 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add "m_" prefix for private member RISC-V: Add "m_" prefix for private member - - - -1- 2023-05-22 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix typo of multiple_rgroup-2.h RISC-V: Fix typo of multiple_rgroup-2.h - - - -1- 2023-05-22 juzhe.zhong@rivai.ai Unresolved
[V13] VECT: Fix bug of multiple-rgroup for length is counting elements [V13] VECT: Fix bug of multiple-rgroup for length is counting elements - - - -1- 2023-05-22 juzhe.zhong@rivai.ai Corrupt patch
RISC-V: Reorganize the code of CONST_VECTOR handling in riscv.cc RISC-V: Reorganize the code of CONST_VECTOR handling in riscv.cc - - - -1- 2023-05-22 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add RVV comparison autovectorization RISC-V: Add RVV comparison autovectorization - - - -1- 2023-05-20 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add mode switching target hook to insert rounding mode config for fixed-point instructions RISC-V: Add mode switching target hook to insert rounding mode config for fixed-point instructions - - - -1- 2023-05-17 juzhe.zhong@rivai.ai Unresolved
RISC-V: Introduce rounding mode operand into fixed-point intrinsics RISC-V: Introduce rounding mode operand into fixed-point intrinsics - - - -1- 2023-05-17 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Add FRM and rounding mode operand into floating point intrinsics [V2] RISC-V: Add FRM and rounding mode operand into floating point intrinsics - - - -1- 2023-05-16 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Add FRM and rounding mode operand into floating point intrinsics [V2] RISC-V: Add FRM and rounding mode operand into floating point intrinsics - - - -1- 2023-05-16 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Add FRM and rounding mode operand into floating point intrinsics [V2] RISC-V: Add FRM and rounding mode operand into floating point intrinsics - - - -1- 2023-05-15 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add rounding mode operand for floating point instructions RISC-V: Add rounding mode operand for floating point instructions - - - -1- 2023-05-15 juzhe.zhong@rivai.ai Unresolved
[V3] RISC-V: Add rounding mode operand for fixed-point patterns [V3] RISC-V: Add rounding mode operand for fixed-point patterns - - - -1- 2023-05-15 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Add rounding mode operand for fixed-point patterns [V2] RISC-V: Add rounding mode operand for fixed-point patterns - - - -1- 2023-05-15 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add rounding mode operand for fixed-point patterns RISC-V: Add rounding mode operand for fixed-point patterns - - - -1- 2023-05-15 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add VECTOR_ALIGNMENT_REACHABLE && BUILTIN_VECTORIZATION_COST target hook to optimize RVV VL… RISC-V: Add VECTOR_ALIGNMENT_REACHABLE && BUILTIN_VECTORIZATION_COST target hook to optimize RVV VL… - - - -1- 2023-05-15 juzhe.zhong@rivai.ai Unresolved
RISC-V: Optimize vsetvl AVL for VLS VLMAX auto-vectorization RISC-V: Optimize vsetvl AVL for VLS VLMAX auto-vectorization - - - -1- 2023-05-13 juzhe.zhong@rivai.ai Unresolved
[V5] RISC-V: Using merge approach to optimize repeating sequence in vec_init [V5] RISC-V: Using merge approach to optimize repeating sequence in vec_init - - - -1- 2023-05-13 juzhe.zhong@rivai.ai Unresolved
[V4] RISC-V: Using merge approach to optimize repeating sequence in vec_init [V4] RISC-V: Using merge approach to optimize repeating sequence in vec_init - - - -1- 2023-05-12 juzhe.zhong@rivai.ai Unresolved
[V3] RISC-V: Using merge approach to optimize repeating sequence in vec_init [V3] RISC-V: Using merge approach to optimize repeating sequence in vec_init - - - -1- 2023-05-12 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Using merge approach to optimize repeating sequence in vec_init [V2] RISC-V: Using merge approach to optimize repeating sequence in vec_init - - - -1- 2023-05-12 juzhe.zhong@rivai.ai Unresolved
RISC-V: Using merge approach to optimize repeating sequence in vec_init RISC-V: Using merge approach to optimize repeating sequence in vec_init - - - -1- 2023-05-12 juzhe.zhong@rivai.ai Unresolved
[commited] MAINTAINERS: Add myself to write after approval [commited] MAINTAINERS: Add myself to write after approval - - - -1- 2023-05-11 juzhe.zhong@rivai.ai Repeat Merge
MAINTAINERS: Add myself to write after approval MAINTAINERS: Add myself to write after approval - - - -1- 2023-05-11 juzhe.zhong@rivai.ai Repeat Merge
RISC-V: Add basic vec_init support for RVV auto-vectorizaiton RISC-V: Add basic vec_init support for RVV auto-vectorizaiton - - - -1- 2023-05-10 juzhe.zhong@rivai.ai Unresolved
[V5] RISC-V: Enable basic RVV auto-vectorization support. [V5] RISC-V: Enable basic RVV auto-vectorization support. - - - -1- 2023-05-05 juzhe.zhong@rivai.ai Unresolved
[V4] RISC-V: Defer vsetvli insertion to later if possible [PR108270] [V4] RISC-V: Defer vsetvli insertion to later if possible [PR108270] - - - -1- 2023-04-21 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support segment intrinsics RISC-V: Support segment intrinsics - - - -1- 2023-04-21 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add tuple type vget/vset intrinsics RISC-V: Add tuple type vget/vset intrinsics - - - -1- 2023-04-19 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add tuple types support RISC-V: Add tuple types support - - - -1- 2023-04-18 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add tuple types support RISC-V: Add tuple types support - - - -1- 2023-04-18 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add tuple type builtins for segment intrinsics RISC-V: Add tuple type builtins for segment intrinsics - - - -1- 2023-04-17 juzhe.zhong@rivai.ai Unresolved
RISC-V: Allow LMUL = 2 auto-vectorization for zve32* RISC-V: Allow LMUL = 2 auto-vectorization for zve32* - - - -1- 2023-04-10 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix EEW = 64 predicate RISC-V: Fix EEW = 64 predicate - - - -1- 2023-04-10 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix incorrect condition of EEW = 64 mode RISC-V: Fix incorrect condition of EEW = 64 mode - - - -1- 2023-04-07 juzhe.zhong@rivai.ai Unresolved
[2/3] RISC-V: Enable basic RVV auto-vectorization and support WHILE_LEN/LEN_LOAD/LEN_STORE pattern RISC-V:Enable basic auto-vectorization for RVV - - - -1- 2023-04-06 juzhe.zhong@rivai.ai Unresolved
[GCC14,QUEUE] RISC-V: Support chunk = 128bit for 'V' Extension [GCC14,QUEUE] RISC-V: Support chunk = 128bit for 'V' Extension - - - -1- 2023-03-31 juzhe.zhong@rivai.ai Unresolved
[GCC14,QUEUE] RISC-V: Eliminate redundant vsetvli for duplicate AVL def [GCC14,QUEUE] RISC-V: Eliminate redundant vsetvli for duplicate AVL def - - - -1- 2023-03-28 juzhe.zhong@rivai.ai Unresolved
RISC-V: Eliminate redundant vsetvli for duplicate AVL def RISC-V: Eliminate redundant vsetvli for duplicate AVL def - - - -1- 2023-03-28 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix ICE in LRA for LMUL < 1 vector spillings RISC-V: Fix ICE in LRA for LMUL < 1 vector spillings - - - -1- 2023-03-22 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fine tune vmadc/vmsbc RA constraint RISC-V: Fine tune vmadc/vmsbc RA constraint - - - -1- 2023-03-16 juzhe.zhong@rivai.ai Unresolved
ISC-V: Fine tune vmadc/vmsbc RA constraint ISC-V: Fine tune vmadc/vmsbc RA constraint - - - -1- 2023-03-16 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix bugs of ternary integer and floating-point ternary intrinsics. RISC-V: Fix bugs of ternary integer and floating-point ternary intrinsics. - - - -1- 2023-03-15 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix bugs of ternary integer and floating-point ternary intrinsics. RISC-V: Fix bugs of ternary integer and floating-point ternary intrinsics. - - - -1- 2023-03-15 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix bugs of ternary integer and floating-point ternary intrinsics. RISC-V: Fix bugs of ternary integer and floating-point ternary intrinsics. - - - -1- 2023-03-14 juzhe.zhong@rivai.ai Unresolved
RISC-V: Refine reduction RA constraint according to RVV ISA RISC-V: Refine reduction RA constraint according to RVV ISA - - - -1- 2023-03-13 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix bugs of internal tests. RISC-V: Fix bugs of internal tests. - - - -1- 2023-03-13 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Add fault first load C/C++ support [V2] RISC-V: Add fault first load C/C++ support - - - -1- 2023-03-08 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fine tunning merge operand constraint RISC-V: Fine tunning merge operand constraint - - - -1- 2023-03-08 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix ICE for avl_single-86/avl_single-88/avl_single-90 RISC-V: Fix ICE for avl_single-86/avl_single-88/avl_single-90 - - - -1- 2023-03-05 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add RVV misc intrinsic support RISC-V: Add RVV misc intrinsic support - - - -1- 2023-03-02 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add permutation C/C++ support RISC-V: Add permutation C/C++ support - - - -1- 2023-02-27 juzhe.zhong@rivai.ai Unresolved
RISC-V: Remove void_type_node of void_args for vsetvlmax intrinsic RISC-V: Remove void_type_node of void_args for vsetvlmax intrinsic - - - -1- 2023-02-27 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add testcase for VSETVL PASS RISC-V: Add testcase for VSETVL PASS - - - -1- 2023-02-24 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add scalar move support and fix VSETVL bugs RISC-V: Add scalar move support and fix VSETVL bugs - - - -1- 2023-02-24 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add RVV reduction C/C++ intrinsics support RISC-V: Add RVV reduction C/C++ intrinsics support - - - -1- 2023-02-20 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add floating-point RVV C/C++ api RISC-V: Add floating-point RVV C/C++ api - - - -1- 2023-02-17 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add RVV all mask C/C++ intrinsics support RISC-V: Add RVV all mask C/C++ intrinsics support - - - -1- 2023-02-16 juzhe.zhong@rivai.ai Unresolved
RISC-V: Rename tu_preds to none_tu_preds [NFC] RISC-V: Rename tu_preds to none_tu_preds [NFC] - - - -1- 2023-02-15 juzhe.zhong@rivai.ai Unresolved
RISC-V: Normalize SEW = 64 handling into a simplified function RISC-V: Normalize SEW = 64 handling into a simplified function - - - -1- 2023-02-15 juzhe.zhong@rivai.ai Unresolved
RISC-V: Move saturating add/subtract md pattern location [NFC] RISC-V: Move saturating add/subtract md pattern location [NFC] - - - -1- 2023-02-14 juzhe.zhong@rivai.ai Unresolved
RISC-V: Rearrange the organization of declarations of RVV intrinsics [NFC] RISC-V: Rearrange the organization of declarations of RVV intrinsics [NFC] - - - -1- 2023-02-14 juzhe.zhong@rivai.ai Unresolved
RISC-V: Remove "extern“ for namespace [NFC] RISC-V: Remove "extern“ for namespace [NFC] - - - -1- 2023-02-14 juzhe.zhong@rivai.ai Unresolved
RISC-V: Replace simm32_p with immediate_operand (Pmode) RISC-V: Replace simm32_p with immediate_operand (Pmode) - - - -1- 2023-02-14 juzhe.zhong@rivai.ai Unresolved
RISC-V: Finish all integer C/C++ intrinsics RISC-V: Finish all integer C/C++ intrinsics - - - -1- 2023-02-14 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add Full 'v' extension predicate to vsmul intrinsic RISC-V: Add Full 'v' extension predicate to vsmul intrinsic - - - -1- 2023-02-10 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add fixed-point support RISC-V: Add fixed-point support - - - -1- 2023-02-10 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add vnsrl/vnsra/vncvt/vmerge/vmv C/C++ support RISC-V: Add vnsrl/vnsra/vncvt/vmerge/vmv C/C++ support - - - -1- 2023-02-09 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add vmadc/vsbc C/C++ API support RISC-V: Add vmadc/vsbc C/C++ API support - - - -1- 2023-02-08 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix indent RISC-V: Fix indent - - - -1- 2023-02-08 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix indent [NFC] RISC-V: Fix indent [NFC] - - - -1- 2023-02-08 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add vadc/vsbc C/C++ API support RISC-V: Add vadc/vsbc C/C++ API support - - - -1- 2023-02-08 juzhe.zhong@rivai.ai Unresolved
RISC-V: allow vx instruction use "zero" as scalar register. RISC-V: allow vx instruction use "zero" as scalar register. - - - -1- 2023-02-07 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add integer widening instructions RISC-V: Add integer widening instructions - - - -1- 2023-02-07 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add vmulh C/C++ support RISC-V: Add vmulh C/C++ support - - - -1- 2023-02-06 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add vsext/vzext C/C++ intrinsic support RISC-V: Add vsext/vzext C/C++ intrinsic support - - - -1- 2023-02-06 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add saturating Addition && Subtraction C/C++ Support RISC-V: Add saturating Addition && Subtraction C/C++ Support - - - -1- 2023-02-05 juzhe.zhong@rivai.ai Unresolved
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