Show patches with: Submitter = juzhe.zhong@rivai.ai       |    State = Action Required       |   652 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
RISC-V: Change MD attribute avl_type into avl_type_idx[NFC] RISC-V: Change MD attribute avl_type into avl_type_idx[NFC] - - - -1- 2023-10-25 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix multiple EXCESS test FAILs in RVV testsuite RISC-V: Fix multiple EXCESS test FAILs in RVV testsuite - - - -1- 2023-10-25 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add AVL propagation PASS for RVV auto-vectorization RISC-V: Add AVL propagation PASS for RVV auto-vectorization - - - -1- 2023-10-24 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Fix ICE of RTL CHECK on VSETVL PASS[PR111947] [Committed] RISC-V: Fix ICE of RTL CHECK on VSETVL PASS[PR111947] - - - -1- 2023-10-24 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Fix ICE for the fusion case from vsetvl to scalar move[PR111927] [V2] RISC-V: Fix ICE for the fusion case from vsetvl to scalar move[PR111927] - - - -1- 2023-10-23 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix ICE for the fusion case from vsetvl to scalar move[PR111927] RISC-V: Fix ICE for the fusion case from vsetvl to scalar move[PR111927] - - - -1- 2023-10-23 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Fix typo[VSETVL PASS] [Committed] RISC-V: Fix typo[VSETVL PASS] - - - -1- 2023-10-23 juzhe.zhong@rivai.ai Unresolved
RISC-V: Rename some variables of vector_block_info[NFC] RISC-V: Rename some variables of vector_block_info[NFC] - - - -1- 2023-10-20 juzhe.zhong@rivai.ai Unresolved
[V5] VECT: Enhance SLP of MASK_LEN_GATHER_LOAD[PR111721] [V5] VECT: Enhance SLP of MASK_LEN_GATHER_LOAD[PR111721] - - - -1- 2023-10-18 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Fix failed hoist in LICM of vmv.v.x instruction [V2] RISC-V: Fix failed hoist in LICM of vmv.v.x instruction - - - -1- 2023-10-18 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix failed hoist in LICM of vmv.v.x instruction RISC-V: Fix failed hoist in LICM of vmv.v.x instruction - - - -1- 2023-10-18 juzhe.zhong@rivai.ai Unresolved
RISC-V: Optimize consecutive permutation index pattern by vrgather.vi/vx RISC-V: Optimize consecutive permutation index pattern by vrgather.vi/vx - - - -1- 2023-10-18 juzhe.zhong@rivai.ai Unresolved
RISC-V: Enable more tests for dynamic LMUL and bug fix[PR111832] RISC-V: Enable more tests for dynamic LMUL and bug fix[PR111832] - - - -1- 2023-10-17 juzhe.zhong@rivai.ai Unresolved
[V4] VECT: Enhance SLP of MASK_LEN_GATHER_LOAD[PR111721] [V4] VECT: Enhance SLP of MASK_LEN_GATHER_LOAD[PR111721] - - - -1- 2023-10-17 juzhe.zhong@rivai.ai Unresolved
[V4] RISC-V: Fix unexpected big LMUL choosing in dynamic LMUL model for non-adjacent load/store [V4] RISC-V: Fix unexpected big LMUL choosing in dynamic LMUL model for non-adjacent load/store - - - -1- 2023-10-16 juzhe.zhong@rivai.ai Unresolved
[V3] RISC-V: Fix unexpected big LMUL choosing in dynamic LMUL model for non-adjacent load/store [V3] RISC-V: Fix unexpected big LMUL choosing in dynamic LMUL model for non-adjacent load/store - - - -1- 2023-10-16 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Fix unexpected big LMUL choosing in dynamic LMUL model for non-adjacent load/store [V2] RISC-V: Fix unexpected big LMUL choosing in dynamic LMUL model for non-adjacent load/store - - - -1- 2023-10-16 juzhe.zhong@rivai.ai Unresolved
RISC-V: Use VLS modes if the NITERS is known and smaller than VLS mode elements. RISC-V: Use VLS modes if the NITERS is known and smaller than VLS mode elements. - - - -1- 2023-10-16 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix unexpected big LMUL choosing in dynamic LMUL model for non-adjacent load/store RISC-V: Fix unexpected big LMUL choosing in dynamic LMUL model for non-adjacent load/store - - - -1- 2023-10-16 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Fix vsingle attribute [Committed] RISC-V: Fix vsingle attribute - - - -1- 2023-10-15 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Remove redundant iterators. [Committed] RISC-V: Remove redundant iterators. - - - -1- 2023-10-14 juzhe.zhong@rivai.ai Unresolved
[V3] VECT: Enhance SLP of MASK_LEN_GATHER_LOAD[PR111721] [V3] VECT: Enhance SLP of MASK_LEN_GATHER_LOAD[PR111721] - - - -1- 2023-10-13 juzhe.zhong@rivai.ai Unresolved
[V2] VECT: Enhance SLP of MASK_LEN_GATHER_LOAD[PR111721] [V2] VECT: Enhance SLP of MASK_LEN_GATHER_LOAD[PR111721] - - - -1- 2023-10-12 juzhe.zhong@rivai.ai Unresolved
VECT: Enhance SLP of MASK_LEN_GATHER_LOAD[PR111721] VECT: Enhance SLP of MASK_LEN_GATHER_LOAD[PR111721] - - - -1- 2023-10-11 juzhe.zhong@rivai.ai Unresolved
[V3] RISC-V: Fix incorrect index(offset) of gather/scatter [V3] RISC-V: Fix incorrect index(offset) of gather/scatter - - - -1- 2023-10-11 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Fix incorrect index(offset) of gather/scatter [V2] RISC-V: Fix incorrect index(offset) of gather/scatter - - - -1- 2023-10-11 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix incorrect index(offset) of gather/scatter RISC-V: Fix incorrect index(offset) of gather/scatter - - - -1- 2023-10-11 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Add VLS BOOL mode vcond_mask[PR111751] [Committed] RISC-V: Add VLS BOOL mode vcond_mask[PR111751] - - - -1- 2023-10-10 juzhe.zhong@rivai.ai Unresolved
RISC-V Regression: Fix FAIL of predcom-2.c RISC-V Regression: Fix FAIL of predcom-2.c - - - -1- 2023-10-10 juzhe.zhong@rivai.ai Unresolved
RISC-V Regression: Fix FAIL of bb-slp-pr65935.c for RVV RISC-V Regression: Fix FAIL of bb-slp-pr65935.c for RVV - - - -1- 2023-10-10 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add available vector size for RVV RISC-V: Add available vector size for RVV - - - -1- 2023-10-09 juzhe.zhong@rivai.ai Unresolved
TEST: Add vectorization check TEST: Add vectorization check - - - -1- 2023-10-09 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Support movmisalign of RVV VLA modes [V2] RISC-V: Support movmisalign of RVV VLA modes - - - -1- 2023-10-09 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support movmisalign of RVV VLA modes RISC-V: Support movmisalign of RVV VLA modes - - - -1- 2023-10-08 juzhe.zhong@rivai.ai Unresolved
RISC-V: Enable more tests of "vect" for RVV RISC-V: Enable more tests of "vect" for RVV - - - -1- 2023-10-07 juzhe.zhong@rivai.ai Unresolved
RISC-V: Remove @ of vec_series RISC-V: Remove @ of vec_series - - - -1- 2023-10-04 juzhe.zhong@rivai.ai Unresolved
[V3] RISC-V: Remove mem-to-mem VLS move pattern[PR111566] [V3] RISC-V: Remove mem-to-mem VLS move pattern[PR111566] - - - -1- 2023-09-26 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Fix mem-to-mem VLS move pattern[PR111566] [V2] RISC-V: Fix mem-to-mem VLS move pattern[PR111566] - - - -1- 2023-09-26 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Fix mem-to-mem VLS move pattern[PR111566] [Committed] RISC-V: Fix mem-to-mem VLS move pattern[PR111566] - - - -1- 2023-09-26 juzhe.zhong@rivai.ai Unresolved
[V2] MATCH: Optimize COND_ADD reduction pattern [V2] MATCH: Optimize COND_ADD reduction pattern - - - -1- 2023-09-26 juzhe.zhong@rivai.ai Unresolved
[V2] MATCH: Optimize COND_ADD_LEN reduction pattern [V2] MATCH: Optimize COND_ADD_LEN reduction pattern - - - -1- 2023-09-26 juzhe.zhong@rivai.ai Unresolved
MATCH: Optimize COND_ADD reduction pattern MATCH: Optimize COND_ADD reduction pattern - - - -1- 2023-09-26 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix AVL/VL bug of VSETVL PASS[PR111548] RISC-V: Fix AVL/VL bug of VSETVL PASS[PR111548] - - - -1- 2023-09-24 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Support full coverage VLS combine support [Committed] RISC-V: Support full coverage VLS combine support - - - -1- 2023-09-24 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Add VLS unary combine patterns [Committed] RISC-V: Add VLS unary combine patterns - - - -1- 2023-09-23 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Remove @ of vec_duplicate pattern [Committed] RISC-V: Remove @ of vec_duplicate pattern - - - -1- 2023-09-22 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add VLS conditional patterns support RISC-V: Add VLS conditional patterns support - - - -1- 2023-09-22 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Add VLS integer ABS support [Committed] RISC-V: Add VLS integer ABS support - - - -1- 2023-09-21 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Support VLS mult high [Committed] RISC-V: Support VLS mult high - - - -1- 2023-09-21 juzhe.zhong@rivai.ai Unresolved
RISC-V: Enable undefined support for RVV auto-vectorization[PR110751] RISC-V: Enable undefined support for RVV auto-vectorization[PR110751] - - - -1- 2023-09-21 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix SUBREG move of VLS mode[PR111486] RISC-V: Fix SUBREG move of VLS mode[PR111486] - - - -1- 2023-09-21 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Support VLS INT <-> FP conversions [Committed] RISC-V: Support VLS INT <-> FP conversions - - - -1- 2023-09-21 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Support VLS floating-point extend/truncate [Committed] RISC-V: Support VLS floating-point extend/truncate - - - -1- 2023-09-20 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Extend VLS modes in 'VWEXTI' iterator [Committed] RISC-V: Extend VLS modes in 'VWEXTI' iterator - - - -1- 2023-09-20 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add FNMS floating-point VLS tests RISC-V: Add FNMS floating-point VLS tests - - - -1- 2023-09-19 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Support VLS unary floating-point patterns [Committed] RISC-V: Support VLS unary floating-point patterns - - - -1- 2023-09-19 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Support VLS floating-point FMA/FNMA/FMS auto-vectorization [Committed] RISC-V: Support VLS floating-point FMA/FNMA/FMS auto-vectorization - - - -1- 2023-09-19 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Support integer FMA/FNMA VLS modes autovectorization [Committed] RISC-V: Support integer FMA/FNMA VLS modes autovectorization - - - -1- 2023-09-19 juzhe.zhong@rivai.ai Unresolved
RISC-V: Remove redundant vec_duplicate pattern RISC-V: Remove redundant vec_duplicate pattern - - - -1- 2023-09-18 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Fix bogus FAILs of vsetvl testcases [Committed] RISC-V: Fix bogus FAILs of vsetvl testcases - - - -1- 2023-09-18 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Support VLS reduction [Committed] RISC-V: Support VLS reduction - - - -1- 2023-09-18 juzhe.zhong@rivai.ai Unresolved
RISC-V: Remove autovec-vls.md file and clean up VLS move modes[NFC] RISC-V: Remove autovec-vls.md file and clean up VLS move modes[NFC] - - - -1- 2023-09-18 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Remove redundant codes of VLS patterns[NFC] [Committed] RISC-V: Remove redundant codes of VLS patterns[NFC] - - - -1- 2023-09-18 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support VLS modes reduction[PR111153] RISC-V: Support VLS modes reduction[PR111153] - - - -1- 2023-09-17 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support VLS modes vec_init auto-vectorization RISC-V: Support VLS modes vec_init auto-vectorization - - - -1- 2023-09-15 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support VLS modes mask operations RISC-V: Support VLS modes mask operations - - - -1- 2023-09-14 juzhe.zhong@rivai.ai Unresolved
[V4] RISC-V: Expand VLS mode to scalar mode move[PR111391] [V4] RISC-V: Expand VLS mode to scalar mode move[PR111391] - - - -1- 2023-09-14 juzhe.zhong@rivai.ai Unresolved
[V3] RISC-V: Expand VLS mode to scalar mode move[PR111391] [V3] RISC-V: Expand VLS mode to scalar mode move[PR111391] - - - -1- 2023-09-14 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Format VSETVL PASS code [Committed] RISC-V: Format VSETVL PASS code - - - -1- 2023-09-14 juzhe.zhong@rivai.ai Unresolved
[V3] RISC-V: Fix ICE in get_avl_or_vl_reg [V3] RISC-V: Fix ICE in get_avl_or_vl_reg - - - -1- 2023-09-14 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Fix ICE in get_avl_or_vl_reg [V2] RISC-V: Fix ICE in get_avl_or_vl_reg - - - -1- 2023-09-14 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix ICE in get_avl_or_vl_reg[PR111395] RISC-V: Fix ICE in get_avl_or_vl_reg[PR111395] - - - -1- 2023-09-14 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Expand VLS mode to scalar mode move[PR111391] [V2] RISC-V: Expand VLS mode to scalar mode move[PR111391] - - - -1- 2023-09-13 juzhe.zhong@rivai.ai Unresolved
RISC-V: Expand VLS mode to scalar mode move[PR111391] RISC-V: Expand VLS mode to scalar mode move[PR111391] - - - -1- 2023-09-13 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support VLS modes VEC_EXTRACT auto-vectorization RISC-V: Support VLS modes VEC_EXTRACT auto-vectorization - - - -1- 2023-09-13 juzhe.zhong@rivai.ai Unresolved
[committed] RISC-V: Remove redundant ABI test [committed] RISC-V: Remove redundant ABI test - - - -1- 2023-09-13 juzhe.zhong@rivai.ai Repeat Merge
[V2] RISC-V: Support VECTOR BOOL vcond_mask optab[PR111337] [V2] RISC-V: Support VECTOR BOOL vcond_mask optab[PR111337] - - - -1- 2023-09-12 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support VECTOR BOOL vcond_mask optab[PR111337] RISC-V: Support VECTOR BOOL vcond_mask optab[PR111337] - - - -1- 2023-09-12 juzhe.zhong@rivai.ai Unresolved
[V5] RISC-V: Support Dynamic LMUL Cost model [V5] RISC-V: Support Dynamic LMUL Cost model - - - -1- 2023-09-12 juzhe.zhong@rivai.ai Unresolved
[V4] RISC-V: Support Dynamic LMUL Cost model [V4] RISC-V: Support Dynamic LMUL Cost model - - - -1- 2023-09-12 juzhe.zhong@rivai.ai Unresolved
[V3] RISC-V: Support Dynamic LMUL Cost model [V3] RISC-V: Support Dynamic LMUL Cost model - - - -1- 2023-09-11 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Support Dynamic LMUL Cost model [V2] RISC-V: Support Dynamic LMUL Cost model - - - -1- 2023-09-11 juzhe.zhong@rivai.ai Unresolved
RISC-V: Remove redundant functions RISC-V: Remove redundant functions - - - -1- 2023-09-11 juzhe.zhong@rivai.ai Unresolved
RISC-V: Use dominance analysis in global vsetvl elimination RISC-V: Use dominance analysis in global vsetvl elimination - - - -1- 2023-09-11 juzhe.zhong@rivai.ai Unresolved
[Committed,V2] RISC-V: Add VLS modes VEC_PERM support[PR111311] [Committed,V2] RISC-V: Add VLS modes VEC_PERM support[PR111311] - - - -1- 2023-09-11 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Add missing VLS mask bool mode reg -> reg patterns [Committed] RISC-V: Add missing VLS mask bool mode reg -> reg patterns - - - -1- 2023-09-11 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Avoid unnecessary slideup in compress pattern of vec_perm [V2] RISC-V: Avoid unnecessary slideup in compress pattern of vec_perm - - - -1- 2023-09-10 juzhe.zhong@rivai.ai Unresolved
RISC-V: Avoid unnecessary slideup in compress pattern of vec_perm RISC-V: Avoid unnecessary slideup in compress pattern of vec_perm - - - -1- 2023-09-10 juzhe.zhong@rivai.ai Unresolved
RISC-V: Expand fixed-vlmax/vls vector permutation in targethook RISC-V: Expand fixed-vlmax/vls vector permutation in targethook - - - -1- 2023-09-10 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix dump FILE of VSETVL PASS[PR111311] RISC-V: Fix dump FILE of VSETVL PASS[PR111311] - - - -1- 2023-09-09 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add VLS modes VEC_PERM support[PR111311] RISC-V: Add VLS modes VEC_PERM support[PR111311] - - - -1- 2023-09-09 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Fix VLS floating-point operations predicate [Committed] RISC-V: Fix VLS floating-point operations predicate - - - -1- 2023-09-09 juzhe.zhong@rivai.ai Unresolved
RISC-V: Suppress bogus warning for VLS types RISC-V: Suppress bogus warning for VLS types - - - -1- 2023-09-08 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix incorrect nregs calculation for VLS modes RISC-V: Fix incorrect nregs calculation for VLS modes - - - -1- 2023-09-08 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add VLS mask modes mov patterns[PR111311] RISC-V: Add VLS mask modes mov patterns[PR111311] - - - -1- 2023-09-07 juzhe.zhong@rivai.ai Unresolved
RISC-V: Remove incorrect earliest vsetvl post optimization[PR111313] RISC-V: Remove incorrect earliest vsetvl post optimization[PR111313] - - - -1- 2023-09-07 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix VSETVL PASS AVL/VL fetch bug[111295] RISC-V: Fix VSETVL PASS AVL/VL fetch bug[111295] - - - -1- 2023-09-06 juzhe.zhong@rivai.ai Unresolved
RISC-V: Remove unreasonable TARGET_64BIT for VLS modes with size = 64bit RISC-V: Remove unreasonable TARGET_64BIT for VLS modes with size = 64bit - - - -1- 2023-09-06 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Support Dynamic LMUL Cost model [V2] RISC-V: Support Dynamic LMUL Cost model - - - -1- 2023-09-05 juzhe.zhong@rivai.ai Unresolved
RISC-V: Export functions as global extern preparing for dynamic LMUL patch use RISC-V: Export functions as global extern preparing for dynamic LMUL patch use - - - -1- 2023-09-05 juzhe.zhong@rivai.ai Unresolved
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