Show patches with: Submitter = juzhe.zhong@rivai.ai       |    State = Action Required       |   652 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
RISC-V: Robostify shuffle index used by vrgather and fix regression RISC-V: Robostify shuffle index used by vrgather and fix regression - - - -1- 2023-12-11 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Fix VLS mode movmiaslign bug [Committed] RISC-V: Fix VLS mode movmiaslign bug - - - -1- 2023-12-09 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support highest overlap for wv instructions RISC-V: Support highest overlap for wv instructions - - - -1- 2023-12-09 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Remove redundant check of better_main_loop_than_p in COST model [Committed] RISC-V: Remove redundant check of better_main_loop_than_p in COST model - - - -1- 2023-12-08 juzhe.zhong@rivai.ai Unresolved
[Committed,V2] RISC-V: Support interleave vector with different step sequence [Committed,V2] RISC-V: Support interleave vector with different step sequence - - - -1- 2023-12-07 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix AVL propagation ICE for vleff/vlsegff RISC-V: Fix AVL propagation ICE for vleff/vlsegff - - - -1- 2023-12-07 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support interleave vector with different step sequence for VLA SLP RISC-V: Support interleave vector with different step sequence for VLA SLP - - - -1- 2023-12-07 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support interleave vector with different step sequence for VLA SLP RISC-V: Support interleave vector with different step sequence for VLA SLP - - - -1- 2023-12-07 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Fix PR112888 ICE [Committed] RISC-V: Fix PR112888 ICE - - - -1- 2023-12-06 juzhe.zhong@rivai.ai Unresolved
[Committed,V2] RISC-V: Fix VSETVL PASS bug [Committed,V2] RISC-V: Fix VSETVL PASS bug - - - -1- 2023-12-06 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix VSETVL PASS bug RISC-V: Fix VSETVL PASS bug - - - -1- 2023-12-06 juzhe.zhong@rivai.ai Unresolved
RISC-V: Block VLSmodes according to TARGET_MAX_LMUL and BITS_PER_RISCV_VECTOR RISC-V: Block VLSmodes according to TARGET_MAX_LMUL and BITS_PER_RISCV_VECTOR - - - -1- 2023-12-05 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add blocker for gather/scatter auto-vectorization RISC-V: Add blocker for gather/scatter auto-vectorization - - - -1- 2023-12-05 juzhe.zhong@rivai.ai Unresolved
[Committed,V2] RISC-V: Fix overlap group incorrect overlap on v0 [Committed,V2] RISC-V: Fix overlap group incorrect overlap on v0 - - - -1- 2023-12-04 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Support highest-number regno overlap for widen ternary [V2] RISC-V: Support highest-number regno overlap for widen ternary - - - -1- 2023-12-04 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support highest-number regno overlap for widen ternary vx instructions RISC-V: Support highest-number regno overlap for widen ternary vx instructions - - - -1- 2023-12-04 juzhe.zhong@rivai.ai Unresolved
RISC-V: Remove earlyclobber from widen reduction RISC-V: Remove earlyclobber from widen reduction - - - -1- 2023-12-04 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix overlap group incorrect overlap on v0 RISC-V: Fix overlap group incorrect overlap on v0 - - - -1- 2023-12-04 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Robostify the W43, W86, W87 constraint enabled attribute [Committed] RISC-V: Robostify the W43, W86, W87 constraint enabled attribute - - - -1- 2023-12-03 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix incorrect combine of extended scalar pattern RISC-V: Fix incorrect combine of extended scalar pattern - - - -1- 2023-12-01 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support highpart register overlap for widen vx/vf instructions RISC-V: Support highpart register overlap for widen vx/vf instructions - - - -1- 2023-12-01 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix VSETVL PASS regression RISC-V: Fix VSETVL PASS regression - - - -1- 2023-12-01 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Remove earlyclobber for wx/wf instructions. [V2] RISC-V: Remove earlyclobber for wx/wf instructions. - - - -1- 2023-11-30 juzhe.zhong@rivai.ai Unresolved
RISC-V: Remove earlyclobber for wx/wf instructions. RISC-V: Remove earlyclobber for wx/wf instructions. - - - -1- 2023-11-30 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Support highpart overlap for floating-point widen instructions [Committed] RISC-V: Support highpart overlap for floating-point widen instructions - - - -1- 2023-11-30 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Rename vconstraint into group_overlap [Committed] RISC-V: Rename vconstraint into group_overlap - - - -1- 2023-11-29 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support highpart overlap for vext.vf RISC-V: Support highpart overlap for vext.vf - - - -1- 2023-11-29 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support highpart register overlap for vwcvt RISC-V: Support highpart register overlap for vwcvt - - - -1- 2023-11-29 juzhe.zhong@rivai.ai Unresolved
RISC-V: Disallow poly (1,1) VLA SLP interleave vectorization RISC-V: Disallow poly (1,1) VLA SLP interleave vectorization - - - -1- 2023-11-28 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix VSETVL PASS regression RISC-V: Fix VSETVL PASS regression - - - -1- 2023-11-27 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Disable AVL propagation of slidedown instructions [Committed] RISC-V: Disable AVL propagation of slidedown instructions - - - -1- 2023-11-26 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Fix typo [Committed] RISC-V: Fix typo - - - -1- 2023-11-26 juzhe.zhong@rivai.ai Unresolved
RISC-V: Remove incorrect function gate gather_scatter_valid_offset_mode_p RISC-V: Remove incorrect function gate gather_scatter_valid_offset_mode_p - - - -1- 2023-11-25 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix inconsistency among all vectorization hooks RISC-V: Fix inconsistency among all vectorization hooks - - - -1- 2023-11-24 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Disable BSWAP optimization for NUNITS < 4 [Committed] RISC-V: Disable BSWAP optimization for NUNITS < 4 - - - -1- 2023-11-24 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Optimize a special case of VLA SLP [V2] RISC-V: Optimize a special case of VLA SLP - - - -1- 2023-11-23 juzhe.zhong@rivai.ai Unresolved
RISC-V: Optimize a special case of VLA SLP RISC-V: Optimize a special case of VLA SLP - - - -1- 2023-11-23 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Add wrapper for emit vec_extract[NFC] [Committed] RISC-V: Add wrapper for emit vec_extract[NFC] - - - -1- 2023-11-23 juzhe.zhong@rivai.ai Unresolved
[Committed,V2] RISC-V: Disable AVL propagation of vrgather instruction [Committed,V2] RISC-V: Disable AVL propagation of vrgather instruction - - - -1- 2023-11-23 juzhe.zhong@rivai.ai Unresolved
RISC-V: Disable AVL propagation of vrgather instruction RISC-V: Disable AVL propagation of vrgather instruction - - - -1- 2023-11-23 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Refine some codes of riscv-v.cc[NFC] [Committed] RISC-V: Refine some codes of riscv-v.cc[NFC] - - - -1- 2023-11-23 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix incorrect use of vcompress in permutation auto-vectorization RISC-V: Fix incorrect use of vcompress in permutation auto-vectorization - - - -1- 2023-11-22 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix permutation indice mode bug RISC-V: Fix permutation indice mode bug - - - -1- 2023-11-22 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Add missing dump check of pr112438.c [Committed] RISC-V: Add missing dump check of pr112438.c - - - -1- 2023-11-21 juzhe.zhong@rivai.ai Unresolved
[BUG,FIX] RISC-V: Disallow COSNT_VECTOR for DI on RV32 [BUG,FIX] RISC-V: Disallow COSNT_VECTOR for DI on RV32 - - - -1- 2023-11-21 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Fix reduc_run-9.c test value check bug [Committed] RISC-V: Fix reduc_run-9.c test value check bug - - - -1- 2023-11-21 juzhe.zhong@rivai.ai Unresolved
[BUG,FIX] RISC-V: Fix intermediate mode on slide1 instruction for SEW64 on RV32 [BUG,FIX] RISC-V: Fix intermediate mode on slide1 instruction for SEW64 on RV32 - - - -1- 2023-11-20 juzhe.zhong@rivai.ai Unresolved
RISC-V Regression: Remove scalable compile option RISC-V Regression: Remove scalable compile option - - - -1- 2023-11-20 juzhe.zhong@rivai.ai Unresolved
[BUG,FIX] RISC-V: Fix VLS DI mode of slide1 instruction attribute [BUG,FIX] RISC-V: Fix VLS DI mode of slide1 instruction attribute - - - -1- 2023-11-20 juzhe.zhong@rivai.ai Unresolved
[Committed,V2] RISC-V: Optimize constant AVL for LRA pattern [Committed,V2] RISC-V: Optimize constant AVL for LRA pattern - - - -1- 2023-11-19 juzhe.zhong@rivai.ai Unresolved
RISC-V: Refactor RVV iterators[NFC] RISC-V: Refactor RVV iterators[NFC] - - - -1- 2023-11-18 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix bug of tuple move splitter[PR112561] RISC-V: Fix bug of tuple move splitter[PR112561] - - - -1- 2023-11-17 juzhe.zhong@rivai.ai Unresolved
RISC-V: Optimize VLA SLP with duplicate VLA shuffle indice RISC-V: Optimize VLA SLP with duplicate VLA shuffle indice - - - -1- 2023-11-17 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support trailing vec_init optimization RISC-V: Support trailing vec_init optimization - - - -1- 2023-11-14 juzhe.zhong@rivai.ai Unresolved
VECT: Add MASK_LEN_STRIDED_LOAD/MASK_LEN_STRIDED_STORE into loop vectorizer VECT: Add MASK_LEN_STRIDED_LOAD/MASK_LEN_STRIDED_STORE into loop vectorizer - - - -1- 2023-11-14 juzhe.zhong@rivai.ai Unresolved
DOC/IFN/OPTAB: Add mask_len_strided_load/mask_len_strided_store DOC/OPTAB/IFN DOC/IFN/OPTAB: Add mask_len_strided_load/mask_len_strided_store DOC/OPTAB/IFN - - - -1- 2023-11-14 juzhe.zhong@rivai.ai Unresolved
[Commit,QUEUE,V3] RISC-V: Support strided load/store [Commit,QUEUE,V3] RISC-V: Support strided load/store - - - -1- 2023-11-14 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Fix init-2.c assembly check [Committed] RISC-V: Fix init-2.c assembly check - - - -1- 2023-11-14 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Adapt VLS init tests [Committed] RISC-V: Adapt VLS init tests - - - -1- 2023-11-13 juzhe.zhong@rivai.ai Unresolved
[Committed,V3] RISC-V: Optimize combine sequence by merge approach [Committed,V3] RISC-V: Optimize combine sequence by merge approach - - - -1- 2023-11-13 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Optimize combine sequence by merge approach [V2] RISC-V: Optimize combine sequence by merge approach - - - -1- 2023-11-13 juzhe.zhong@rivai.ai Unresolved
RISC-V: Optimize combine sequence by merge approach RISC-V: Optimize combine sequence by merge approach - - - -1- 2023-11-13 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add combine optimization by slideup for vec_init vectorization RISC-V: Add combine optimization by slideup for vec_init vectorization - - - -1- 2023-11-10 juzhe.zhong@rivai.ai Unresolved
RISC-V: Robustify vec_init pattern[NFC] RISC-V: Robustify vec_init pattern[NFC] - - - -1- 2023-11-10 juzhe.zhong@rivai.ai Unresolved
RISC-V: Move cond_copysign from combine pattern to autovec pattern RISC-V: Move cond_copysign from combine pattern to autovec pattern - - - -1- 2023-11-09 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix dynamic LMUL cost model ICE RISC-V: Fix dynamic LMUL cost model ICE - - - -1- 2023-11-09 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Fix dynamic tests [NFC] [Committed] RISC-V: Fix dynamic tests [NFC] - - - -1- 2023-11-09 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Fix VSETVL VL check condition bug [Committed] RISC-V: Fix VSETVL VL check condition bug - - - -1- 2023-11-08 juzhe.zhong@rivai.ai Unresolved
RISC-V: Normalize user vsetvl intrinsics[PR112092] RISC-V: Normalize user vsetvl intrinsics[PR112092] - - - -1- 2023-11-08 juzhe.zhong@rivai.ai Unresolved
[V3] test: Fix FAIL of pr97428.c for RVV [V3] test: Fix FAIL of pr97428.c for RVV - - - -1- 2023-11-07 juzhe.zhong@rivai.ai Unresolved
test: Recover sdiv_pow2 check and remove test of RISC-V test: Recover sdiv_pow2 check and remove test of RISC-V - - - -1- 2023-11-07 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Early expand DImode vec_duplicate in RV32 system [V2] RISC-V: Early expand DImode vec_duplicate in RV32 system - - - -1- 2023-11-06 juzhe.zhong@rivai.ai Unresolved
RISC-V: Early expand DImode vec_duplicate in RV32 system RISC-V: Early expand DImode vec_duplicate in RV32 system - - - -1- 2023-11-06 juzhe.zhong@rivai.ai Unresolved
[V2] VECT: Support mask_len_strided_load/mask_len_strided_store in loop vectorize [V2] VECT: Support mask_len_strided_load/mask_len_strided_store in loop vectorize - - - -1- 2023-11-06 juzhe.zhong@rivai.ai Unresolved
[V2] VECT: Support mask_len_strided_load/mask_len_strided_store in loop vectorize [V2] VECT: Support mask_len_strided_load/mask_len_strided_store in loop vectorize - - - -1- 2023-11-06 juzhe.zhong@rivai.ai Unresolved
RISC-V: Enhance AVL propagation for complicate reduction auto-vectorization RISC-V: Enhance AVL propagation for complicate reduction auto-vectorization - - - -1- 2023-11-06 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Fix bug of vlds attribute [Committed] RISC-V: Fix bug of vlds attribute - - - -1- 2023-11-05 juzhe.zhong@rivai.ai Unresolved
OPTAB: Add mask_len_strided_load/mask_len_strided_store optab OPTAB: Add mask_len_strided_load/mask_len_strided_store optab - - - -1- 2023-11-03 juzhe.zhong@rivai.ai Unresolved
[tree-optimization/111721,V2] VECT: Support SLP for MASK_LEN_GATHER_LOAD with dummy mask [tree-optimization/111721,V2] VECT: Support SLP for MASK_LEN_GATHER_LOAD with dummy mask - - - -1- 2023-11-03 juzhe.zhong@rivai.ai Unresolved
[Committed,V3] RISC-V: Fix redundant vsetvl in fixed-vlmax vectorized codes[PR112326] [Committed,V3] RISC-V: Fix redundant vsetvl in fixed-vlmax vectorized codes[PR112326] - - - -1- 2023-11-03 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix bug of AVL propagation PASS RISC-V: Fix bug of AVL propagation PASS - - - -1- 2023-11-02 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Fix redundant vsetvl in fixed-vlmax vectorized codes[PR112326] [V2] RISC-V: Fix redundant vsetvl in fixed-vlmax vectorized codes[PR112326] - - - -1- 2023-11-02 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix redundant vsetvl in fixed-vlmax vectorized codes[PR112326] RISC-V: Fix redundant vsetvl in fixed-vlmax vectorized codes[PR112326] - - - -1- 2023-11-02 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Fix redundant attributes [Committed] RISC-V: Fix redundant attributes - - - -1- 2023-11-02 juzhe.zhong@rivai.ai Unresolved
[tree-optimization/111721] VECT: Support SLP for MASK_LEN_GATHER_LOAD with dummy mask [tree-optimization/111721] VECT: Support SLP for MASK_LEN_GATHER_LOAD with dummy mask - - - -1- 2023-11-02 juzhe.zhong@rivai.ai Unresolved
RISC-V: Allow dest operand and accumulator operand overlap of widen reduction instruction[PR112327] RISC-V: Allow dest operand and accumulator operand overlap of widen reduction instruction[PR112327] - - - -1- 2023-11-01 juzhe.zhong@rivai.ai Unresolved
[Commit,Pending,V2] RISC-V: Support strided load/store [Commit,Pending,V2] RISC-V: Support strided load/store - - - -1- 2023-11-01 juzhe.zhong@rivai.ai Unresolved
[Committed] NFC: Fix whitespace [Committed] NFC: Fix whitespace - - - -1- 2023-11-01 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support strided load/store RISC-V: Support strided load/store - - - -1- 2023-10-31 juzhe.zhong@rivai.ai Unresolved
VECT: Support mask_len_strided_load/mask_len_strided_store in loop vectorize VECT: Support mask_len_strided_load/mask_len_strided_store in loop vectorize - - - -1- 2023-10-31 juzhe.zhong@rivai.ai Unresolved
[V2] OPTABS/IFN: Add mask_len_strided_load/mask_len_strided_store OPTABS/IFN [V2] OPTABS/IFN: Add mask_len_strided_load/mask_len_strided_store OPTABS/IFN - - - -1- 2023-10-31 juzhe.zhong@rivai.ai Unresolved
OPTABS/IFN: Add mask_len_strided_load/mask_len_strided_store OPTABS/IFN OPTABS/IFN: Add mask_len_strided_load/mask_len_strided_store OPTABS/IFN - - - -1- 2023-10-30 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix bugs of handling scalar of SEW64 vx instruction in RV32 RISC-V: Fix bugs of handling scalar of SEW64 vx instruction in RV32 - - - -1- 2023-10-28 juzhe.zhong@rivai.ai Unresolved
[NFC] RISC-V: Move lmul calculation into macro [NFC] RISC-V: Move lmul calculation into macro - - - -1- 2023-10-26 juzhe.zhong@rivai.ai Unresolved
VECT: Support SLP MASK_LEN_GATHER_LOAD with conditional mask VECT: Support SLP MASK_LEN_GATHER_LOAD with conditional mask - - - -1- 2023-10-26 juzhe.zhong@rivai.ai Unresolved
[V2] DOC: Update COND_LEN document [V2] DOC: Update COND_LEN document - - - -1- 2023-10-26 juzhe.zhong@rivai.ai Unresolved
[Ready,to,commit,V3] RISC-V: Add AVL propagation PASS for RVV auto-vectorization [Ready,to,commit,V3] RISC-V: Add AVL propagation PASS for RVV auto-vectorization - - 2 -1- 2023-10-26 juzhe.zhong@rivai.ai Unresolved
DOC: Update COND_LEN document DOC: Update COND_LEN document - - - -1- 2023-10-26 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Add AVL propagation PASS for RVV auto-vectorization [V2] RISC-V: Add AVL propagation PASS for RVV auto-vectorization - - - -1- 2023-10-25 juzhe.zhong@rivai.ai Unresolved
RISC-V: Export some functions from riscv-vsetvl to riscv-v RISC-V: Export some functions from riscv-vsetvl to riscv-v - - - -1- 2023-10-25 juzhe.zhong@rivai.ai Unresolved
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