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Patch
Series
A/R/T
S/W/F
Date
Submitter
Delegate
State
[v2,2/4] LoongArch: Rename ISA_BASE_LA64V100 to ISA_BASE_LA64
Adjust option handling code
- - -
-
1
-
2024-01-08
Yang Yujie
Unresolved
[v2,1/4] LoongArch: Handle ISA evolution switches along with other options
Adjust option handling code
- - -
-
1
-
2024-01-08
Yang Yujie
Unresolved
[committed] RISC-V: Fix avl-type operand index error for ZVBC
[committed] RISC-V: Fix avl-type operand index error for ZVBC
- - -
-
1
-
2024-01-08
Feng Wang
Unresolved
RISC-V: Also handle sign extension in branch costing
RISC-V: Also handle sign extension in branch costing
- - -
-
1
-
2024-01-08
Maciej W. Rozycki
Unresolved
libstdc++: reduce std::variant template instantiation depth
libstdc++: reduce std::variant template instantiation depth
- - -
-
1
-
2024-01-07
Patrick Palka
Unresolved
[avr,applied] Fix some avr test cases
[avr,applied] Fix some avr test cases
- - -
-
1
-
2024-01-07
Georg-Johann Lay
Unresolved
GCN: Add pre-initial support for gfx1100
GCN: Add pre-initial support for gfx1100
- - -
-
1
-
2024-01-07
Tobias Burnus
Unresolved
[committed] Fix typo in last change
[committed] Fix typo in last change
- - -
-
1
-
2024-01-07
Jeff Law
Unresolved
[testsuite,applied] PR52641 Fix more fallout from sloppy tests.
[testsuite,applied] PR52641 Fix more fallout from sloppy tests.
- - -
-
1
-
2024-01-07
Georg-Johann Lay
Unresolved
[testsuite,applied] PR52641: Fix more fallout from sloppy tests.
[testsuite,applied] PR52641: Fix more fallout from sloppy tests.
- - -
-
1
-
2024-01-07
Georg-Johann Lay
Unresolved
[Committed] RISC-V: Use MAX instead of std::max [VSETVL PASS]
[Committed] RISC-V: Use MAX instead of std::max [VSETVL PASS]
- - -
-
1
-
2024-01-07
juzhe.zhong@rivai.ai
Unresolved
[v8,3/4] c++: P0847R7 (deducing this) - diagnostics. [PR102609]
[v8,1/4] c++: P0847R7 (deducing this) - prerequisite changes. [PR102609]
- - -
-
1
-
2024-01-07
waffl3x
Unresolved
[v8,1/4] c++: P0847R7 (deducing this) - prerequisite changes. [PR102609]
[v8,1/4] c++: P0847R7 (deducing this) - prerequisite changes. [PR102609]
- - -
-
1
-
2024-01-07
waffl3x
Unresolved
[8/8] OpenMP: Update documentation of metadirective implementation status.
OpenMP: Implement metadirective support
- - -
-
1
-
2024-01-06
Sandra Loosemore
Unresolved
[7/8] OpenMP: Fortran front-end support for metadirectives.
OpenMP: Implement metadirective support
- - -
-
1
-
2024-01-06
Sandra Loosemore
Unresolved
[6/8] OpenMP: common c/c++ testcases for metadirectives
OpenMP: Implement metadirective support
- - -
-
1
-
2024-01-06
Sandra Loosemore
Unresolved
[5/8] OpenMP: C++ front-end support for metadirectives
OpenMP: Implement metadirective support
- - -
-
1
-
2024-01-06
Sandra Loosemore
Unresolved
[4/8] OpenMP: C front end support for metadirectives
OpenMP: Implement metadirective support
- - -
-
1
-
2024-01-06
Sandra Loosemore
Unresolved
[3/8] libgomp: runtime support for target_device selector
OpenMP: Implement metadirective support
- - -
-
1
-
2024-01-06
Sandra Loosemore
Unresolved
[2/8] OpenMP: middle-end support for metadirectives
OpenMP: Implement metadirective support
- - -
-
1
-
2024-01-06
Sandra Loosemore
Unresolved
[1/8] OpenMP: metadirective tree data structures and front-end interfaces
OpenMP: Implement metadirective support
- - -
-
1
-
2024-01-06
Sandra Loosemore
Unresolved
[testsuite,applied] PR52641: Fix more sloppy tests
[testsuite,applied] PR52641: Fix more sloppy tests
- - -
-
1
-
2024-01-06
Georg-Johann Lay
Unresolved
[Patch, fortran PR89645/99065 No IMPLICIT type error with: ASSOCIATE( X => function() )
[Patch, fortran PR89645/99065 No IMPLICIT type error with: ASSOCIATE( X => function() )
- - -
-
1
-
2024-01-06
Paul Richard Thomas
Unresolved
[v2] libstdc++: Add Unicode-aware width estimation for std::format
[v2] libstdc++: Add Unicode-aware width estimation for std::format
- - -
-
1
-
2024-01-06
Jonathan Wakely
Unresolved
[x86] PR target/113231: Improved costs in Scalar-To-Vector (STV) pass.
[x86] PR target/113231: Improved costs in Scalar-To-Vector (STV) pass.
- - -
-
1
-
2024-01-06
Roger Sayle
Unresolved
vect: Fix ICE in vect_analyze_loop_costing [PR113210]
vect: Fix ICE in vect_analyze_loop_costing [PR113210]
- - -
-
1
-
2024-01-06
Jakub Jelinek
Unresolved
[3/3] LoongArch: Redundant sign extension elimination optimization 2.
[1/3] LoongArch: Optimized some of the symbolic expansion instructions generated during bitwise ope…
- - -
-
1
-
2024-01-06
chenglulu
Unresolved
[2/3] LoongArch: Redundant sign extension elimination optimization.
[1/3] LoongArch: Optimized some of the symbolic expansion instructions generated during bitwise ope…
- - -
-
1
-
2024-01-06
chenglulu
Unresolved
gimplify: Fix ICE in recalculate_side_effects [PR113228]
gimplify: Fix ICE in recalculate_side_effects [PR113228]
- - -
-
1
-
2024-01-06
Jakub Jelinek
Unresolved
[Committed] RISC-V: Update MAX_SEW for available vsevl info[VSETVL PASS]
[Committed] RISC-V: Update MAX_SEW for available vsevl info[VSETVL PASS]
- - -
-
1
-
2024-01-06
juzhe.zhong@rivai.ai
Unresolved
[v3,8/8] libstdc++: Optimize std::is_unbounded_array compilation performance
Optimize more type traits
- - -
-
1
-
2024-01-06
Ken Matsui
Unresolved
[v3,7/8] c++: Implement __is_unbounded_array built-in trait
Optimize more type traits
- - -
-
1
-
2024-01-06
Ken Matsui
Unresolved
[v3,6/8] libstdc++: Optimize std::is_pointer compilation performance
Optimize more type traits
- - -
-
1
-
2024-01-06
Ken Matsui
Unresolved
[v3,5/8] c++: Implement __is_pointer built-in trait
Optimize more type traits
- - -
-
1
-
2024-01-06
Ken Matsui
Unresolved
[v3,4/8] libstdc++: Optimize std::is_volatile compilation performance
Optimize more type traits
- - -
-
1
-
2024-01-06
Ken Matsui
Unresolved
[v3,3/8] c++: Implement __is_volatile built-in trait
Optimize more type traits
- - -
-
1
-
2024-01-06
Ken Matsui
Unresolved
[v3,2/8] libstdc++: Optimize std::is_const compilation performance
Optimize more type traits
- - -
-
1
-
2024-01-06
Ken Matsui
Unresolved
[v3,1/8] c++: Implement __is_const built-in trait
Optimize more type traits
- - -
-
1
-
2024-01-06
Ken Matsui
Unresolved
[Committed,V2] RISC-V: Teach liveness computation loop invariant shift amount
[Committed,V2] RISC-V: Teach liveness computation loop invariant shift amount
- - -
-
1
-
2024-01-06
juzhe.zhong@rivai.ai
Unresolved
[Committed,V2] RISC-V: Allow simplification non-vlmax with len = NUNITS reg to reg move
[Committed,V2] RISC-V: Allow simplification non-vlmax with len = NUNITS reg to reg move
- - -
-
1
-
2024-01-06
juzhe.zhong@rivai.ai
Unresolved
Repost [PATCH 6/6] PowerPC: Add support for 1,024 bit DMR registers.
Repost [PATCH 6/6] PowerPC: Add support for 1,024 bit DMR registers.
- - -
-
1
-
2024-01-05
Michael Meissner
Unresolved
Repost [PATCH 5/6] PowerPC: Switch to dense math names for all MMA operations.
Repost [PATCH 5/6] PowerPC: Switch to dense math names for all MMA operations.
- - -
-
1
-
2024-01-05
Michael Meissner
Unresolved
Repost [PATCH 4/6] PowerPC: Make MMA insns support DMR registers.
Repost [PATCH 4/6] PowerPC: Make MMA insns support DMR registers.
- - -
-
1
-
2024-01-05
Michael Meissner
Unresolved
Repost [PATCH 3/6] PowerPC: Add support for accumulators in DMR registers.
Repost [PATCH 3/6] PowerPC: Add support for accumulators in DMR registers.
- - -
-
1
-
2024-01-05
Michael Meissner
Unresolved
Repost [PATCH 2/6] PowerPC: Make -mcpu=future enable -mblock-ops-vector-pair.
Repost [PATCH 2/6] PowerPC: Make -mcpu=future enable -mblock-ops-vector-pair.
- - -
-
1
-
2024-01-05
Michael Meissner
Unresolved
Repost [PATCH 1/6] Add -mcpu=future
Repost [PATCH 1/6] Add -mcpu=future
- - -
-
1
-
2024-01-05
Michael Meissner
Unresolved
omp_target_is_accessible (was: [patch] libgomp.texi: Document omp_display_env)
omp_target_is_accessible (was: [patch] libgomp.texi: Document omp_display_env)
- - -
-
1
-
2024-01-05
Tobias Burnus
Unresolved
[v2,2/2] arm: Add support for MVE Tail-Predicated Low Overhead Loops
arm: Add support for MVE Tail-Predicated Low Overhead Loops
- - -
-
1
-
2024-01-05
Andre Vieira (lists)
Unresolved
libgccjit: Add support for setting the comment ident
libgccjit: Add support for setting the comment ident
- - -
-
1
-
2024-01-05
Antoni Boucher
Unresolved
aarch64: Rework uxtl->zip optimisation [PR113196]
aarch64: Rework uxtl->zip optimisation [PR113196]
- - -
-
1
-
2024-01-05
Richard Sandiford
Unresolved
[pushed] aarch64: Extend VECT_COMPARE_COSTS to !SVE [PR113104]
[pushed] aarch64: Extend VECT_COMPARE_COSTS to !SVE [PR113104]
- - -
-
1
-
2024-01-05
Richard Sandiford
Unresolved
[committed] libstdc++: Avoid overflow when appending to std::filesystem::path
[committed] libstdc++: Avoid overflow when appending to std::filesystem::path
- - -
-
1
-
2024-01-05
Jonathan Wakely
Unresolved
libstdc++: Add Unicode-aware width estimation for std::format
libstdc++: Add Unicode-aware width estimation for std::format
- - -
-
1
-
2024-01-05
Jonathan Wakely
Unresolved
LoongArch: Implement option save/restore
LoongArch: Implement option save/restore
- - -
-
1
-
2024-01-05
Yang Yujie
Unresolved
[committed] libstdc++: Remove UB from month and weekday additions and subtractions.
[committed] libstdc++: Remove UB from month and weekday additions and subtractions.
- - -
-
1
-
2024-01-05
Jonathan Wakely
Unresolved
RISC-V: Fix avl-type operand index error for ZVBC
RISC-V: Fix avl-type operand index error for ZVBC
- - -
-
1
-
2024-01-05
Feng Wang
Unresolved
[v7,1/2] RISC-V: Add crypto vector builtin function.
[v7,1/2] RISC-V: Add crypto vector builtin function.
- - -
-
1
-
2024-01-05
Feng Wang
Unresolved
[committed] RISC-V: Clean up unused variable [NFC]
[committed] RISC-V: Clean up unused variable [NFC]
- - -
-
1
-
2024-01-05
Kito Cheng
Unresolved
[committed] RISC-V: Clean up testsuite for multi-lib testing [NFC]
[committed] RISC-V: Clean up testsuite for multi-lib testing [NFC]
- - -
-
1
-
2024-01-05
Kito Cheng
Unresolved
[v3,2/2] LoongArch: When the code model is extreme, the symbol address is obtained through macro in…
When cmodel=extreme, add macro support and only support macros.
- - -
-
1
-
2024-01-05
chenglulu
Unresolved
[v3,1/2] LoongArch: Add the macro implementation of mcmodel=extreme.
When cmodel=extreme, add macro support and only support macros.
- - -
-
1
-
2024-01-05
chenglulu
Unresolved
LoongArch: Implenment vec_init<M><N> where N is a LSX vector mode
LoongArch: Implenment vec_init<M><N> where N is a LSX vector mode
- - -
-
1
-
2024-01-05
Jiahao Xu
Unresolved
LoongArch: Improve lasx_xvpermi_q_<LASX:mode> insn pattern
LoongArch: Improve lasx_xvpermi_q_<LASX:mode> insn pattern
- - -
-
1
-
2024-01-05
Jiahao Xu
Unresolved
[2/2] sparc: Add errata workaround to membar patterns
sparc: Char arrays are 64-bit aligned on SPARC
- - -
-
1
-
2024-01-05
Daniel Cederman
Unresolved
[4/4] LoongArch: Simplify -mexplicit-reloc definitions
LoongArch: Adjust option handling code (1st patchset)
- - -
-
1
-
2024-01-05
Yang Yujie
Unresolved
[3/4] LoongArch: Use enums for constants
LoongArch: Adjust option handling code (1st patchset)
- - -
-
1
-
2024-01-05
Yang Yujie
Unresolved
[2/4] LoongArch: Rename ISA_BASE_LA64V100 to ISA_BASE_LA64
LoongArch: Adjust option handling code (1st patchset)
- - -
-
1
-
2024-01-05
Yang Yujie
Unresolved
[1/4] LoongArch: Handle ISA evolution switches along with other options
LoongArch: Adjust option handling code (1st patchset)
- - -
-
1
-
2024-01-05
Yang Yujie
Unresolved
[v3] LoongArch: testsuite:Added support for vector object detection.
[v3] LoongArch: testsuite:Added support for vector object detection.
- - -
-
1
-
2024-01-05
chenxiaolong
Unresolved
RISC-V: Allow simplification non-vlmax with len = NUNITS reg to reg move
RISC-V: Allow simplification non-vlmax with len = NUNITS reg to reg move
- - -
-
1
-
2024-01-05
juzhe.zhong@rivai.ai
Unresolved
[v2,7/7] LoongArch: testsuite:Give up the detection of the gcc.dg/fma-{3, 4, 6, 7}.c file.
LoongArch:Enable testing for common
- - -
-
1
-
2024-01-05
chenxiaolong
Unresolved
[v2,6/7] LoongArch: testsuite:Added additional vectorization "-mlasx" compilation option.
LoongArch:Enable testing for common
- - -
-
1
-
2024-01-05
chenxiaolong
Unresolved
[v2,5/7] LoongArch: testsuite:Delete the default run behavior in pr60510.f.
LoongArch:Enable testing for common
- - -
-
1
-
2024-01-05
chenxiaolong
Unresolved
[v2,4/7] LoongArch: testsuite:Fix FAIL in file bind_c_array_params_2.f90.
LoongArch:Enable testing for common
- - -
-
1
-
2024-01-05
chenxiaolong
Unresolved
[v2,3/7] LoongArch: testsuite:Added detection support for LoongArch architecture in vect-{82, 83}.c.
LoongArch:Enable testing for common
- - -
-
1
-
2024-01-05
chenxiaolong
Unresolved
[v2,2/7] LoongArch: testsuite:Modify the test behavior of the vect-bic-bitmask-{12, 23}.c file.
LoongArch:Enable testing for common
- - -
-
1
-
2024-01-05
chenxiaolong
Unresolved
[v2,1/7] LoongArch: testsuite:Added support for vector object detection.
LoongArch:Enable testing for common
- - -
-
1
-
2024-01-05
chenxiaolong
Unresolved
[v2,2/2] LoongArch: When the code model is extreme, the symbol address is obtained through macro in…
When cmodel=extreme, add macro support and only support macros.
- - -
-
1
-
2024-01-05
chenglulu
Unresolved
[v2,1/2] LoongArch: Add the macro implementation of mcmodel=extreme.
When cmodel=extreme, add macro support and only support macros.
- - -
-
1
-
2024-01-05
chenglulu
Unresolved
RISC-V: Teach liveness computation loop invariant shift amount[Dynamic LMUL]
RISC-V: Teach liveness computation loop invariant shift amount[Dynamic LMUL]
- - -
-
1
-
2024-01-05
juzhe.zhong@rivai.ai
Unresolved
[v2] libgfortran: Bugfix if not define HAVE_ATOMIC_FETCH_ADD
[v2] libgfortran: Bugfix if not define HAVE_ATOMIC_FETCH_ADD
- - -
-
1
-
2024-01-05
Lipeng Zhu
Unresolved
[committed] RISC-V: Add crypto vector builtin function.
[committed] RISC-V: Add crypto vector builtin function.
- - -
-
1
-
2024-01-05
Feng Wang
Unresolved
[5/4] libbacktrace: improve getting debug information for loaded dlls
[1/4] libbacktrace: change all pc related variables to uintptr_t
- - -
-
1
-
2024-01-04
Björn Schäpers
Unresolved
[pushed,2/2] libstdc++: fix typo in <generator>
[pushed,1/2] libstdc++: rename _A badname in <generator>
- - -
-
1
-
2024-01-04
Arsen Arsenović
Unresolved
[pushed,1/2] libstdc++: rename _A badname in <generator>
[pushed,1/2] libstdc++: rename _A badname in <generator>
- - -
-
1
-
2024-01-04
Arsen Arsenović
Unresolved
[COMMITTED] libcpp: add function to check XID properties
[COMMITTED] libcpp: add function to check XID properties
- - -
-
1
-
2024-01-04
Arthur Cohen
Unresolved
contrib: Remove C-style comments from Python files
contrib: Remove C-style comments from Python files
- - -
-
1
-
2024-01-04
Jonathan Wakely
Unresolved
[pushed] analyzer: add sarif properties for checker events
[pushed] analyzer: add sarif properties for checker events
- - -
-
1
-
2024-01-04
David Malcolm
Unresolved
[pushed] analyzer: handle arrays of unknown size in access diagrams [PR113222]
[pushed] analyzer: handle arrays of unknown size in access diagrams [PR113222]
- - -
-
1
-
2024-01-04
David Malcolm
Unresolved
[Committed,V3] RISC-V: Make liveness estimation be aware of .vi variant
[Committed,V3] RISC-V: Make liveness estimation be aware of .vi variant
- - -
-
1
-
2024-01-04
juzhe.zhong@rivai.ai
Unresolved
scev: Avoid ICE on results used in abnormal PHI args [PR113201]
scev: Avoid ICE on results used in abnormal PHI args [PR113201]
- - -
-
1
-
2024-01-04
Jakub Jelinek
Unresolved
[v4] RISC-V: Introduce XTheadVector as a subset of V1.0.0
[v4] RISC-V: Introduce XTheadVector as a subset of V1.0.0
- - -
-
1
-
2024-01-04
joshua
Unresolved
Improve __builtin_popcount* (x) == 1 generation if x is known != 0 [PR90693]
Improve __builtin_popcount* (x) == 1 generation if x is known != 0 [PR90693]
- - -
-
1
-
2024-01-04
Jakub Jelinek
Repeat Merge
lower-bitint: Fix up lowering of huge _BitInt 0 PHI args [PR113120]
lower-bitint: Fix up lowering of huge _BitInt 0 PHI args [PR113120]
- - -
-
1
-
2024-01-04
Jakub Jelinek
Unresolved
lower-bitint: Punt .*_OVERFLOW optimization if cast from IMAGPART_EXPR appears before REALPART_EXPR…
lower-bitint: Punt .*_OVERFLOW optimization if cast from IMAGPART_EXPR appears before REALPART_EXPR…
- - -
-
1
-
2024-01-04
Jakub Jelinek
Unresolved
[Committed,V2] RISC-V: Make liveness estimation be aware of .vi variant
[Committed,V2] RISC-V: Make liveness estimation be aware of .vi variant
- - -
-
1
-
2024-01-04
juzhe.zhong@rivai.ai
Unresolved
RISC-V: Teach liveness estimation be aware of .vi variant
RISC-V: Teach liveness estimation be aware of .vi variant
- - -
-
1
-
2024-01-04
juzhe.zhong@rivai.ai
Unresolved
[Committed] RISC-V: Refine LMUL computation for MASK_LEN_LOAD/MASK_LEN_STORE IFN
[Committed] RISC-V: Refine LMUL computation for MASK_LEN_LOAD/MASK_LEN_STORE IFN
- - -
-
1
-
2024-01-04
juzhe.zhong@rivai.ai
Unresolved
[committed,obvious] OpenMP: trivial cleanups to omp-general.cc
[committed,obvious] OpenMP: trivial cleanups to omp-general.cc
- - -
-
1
-
2024-01-04
Sandra Loosemore
Unresolved
LoongArch: Fixed the problem of incorrect judgment of the immediate field of the [x]vld/[x]vst inst…
LoongArch: Fixed the problem of incorrect judgment of the immediate field of the [x]vld/[x]vst inst…
- - -
-
1
-
2024-01-04
chenglulu
Unresolved
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