mbox series

[RFC,0/1] RISC-V: Make SHA-256, SM3 and SM4 builtins operate on uint32_t

Message ID cover.1694134824.git.research_trasio@irq.a4lg.com
Headers
Series RISC-V: Make SHA-256, SM3 and SM4 builtins operate on uint32_t |

Message

Tsukasa OI Sept. 8, 2023, 1:03 a.m. UTC 
  Hi,

This is built on another RFC PATCH "RISC-V: Change RISC-V bit manipulation
/ scalar crypto builtin types" and changes SHA-256, SM3 and SM4 intrinsics
operate on uint32_t, not on XLEN-bit wide integers.

This is in parity with the LLVM commit 599421ae36c3 ("[RISCV] Re-define
sha256, Zksed, and Zksh intrinsics to use i32 types.") by Craig Topper.

Because we had to refine the base instruction definitions, it was way harder
than that of LLVM.  Thankfully, we have a similar example: 32-bit integer
instructions on RV64 such as ADDW.

Before:
   riscv_<op>_si: For RV32, fully operate on uint32_t
   riscv_<op>_di: For RV64, fully operate on uint64_t
After:
  *riscv_<op>_si: For RV32, fully operate on uint32_t
   riscv_<op>_di_extended:
                  For RV64, input is uint32_t and output is int64_t,
                  sign-extended from the int32_t result
                  (represents a part of <op> behavior).
   riscv_<op>_si: Common (fully operate on uint32_t).
                  On RV32, expands to *riscv_<op>_si.
                  On RV64, initially expands to riscv_<op>_di_extended *and*
                  extracts lower 32-bits from the int64_t result.

Sincerely,
Tsukasa




Tsukasa OI (1):
  RISC-V: Make SHA-256, SM3 and SM4 builtins operate on uint32_t

 gcc/config/riscv/crypto.md                    | 161 ++++++++++++------
 gcc/config/riscv/riscv-builtins.cc            |   7 +-
 gcc/config/riscv/riscv-ftypes.def             |   1 -
 gcc/config/riscv/riscv-scalar-crypto.def      |  24 +--
 .../gcc.target/riscv/zknh-sha256-32.c         |  10 ++
 .../riscv/{zknh-sha256.c => zknh-sha256-64.c} |   8 +-
 gcc/testsuite/gcc.target/riscv/zksed64.c      |   4 +-
 gcc/testsuite/gcc.target/riscv/zksh64.c       |   4 +-
 8 files changed, 139 insertions(+), 80 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha256-32.c
 rename gcc/testsuite/gcc.target/riscv/{zknh-sha256.c => zknh-sha256-64.c} (78%)


base-commit: daaed758517c81fc8f8bc6502be648aca51ab278
prerequisite-patch-id: 4f4a84ebc0c33ea159db4dcd70fa8894f27c638a
prerequisite-patch-id: d2b85f777b042d349c5e232979ee219c8147c154