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[8.43.85.97]) by mx.google.com with ESMTPS id dc12-20020a170906c7cc00b0094f4c62e2aesi1052141ejb.278.2023.05.05.02.45.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 02:45:37 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@oss-cipunited-com.20200927.dkim.feishu.cn header.s=s1 header.b="XNfC/SAZ"; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 420E43895FD7 for ; Fri, 5 May 2023 09:42:47 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from t03.bc.larksuite.com (t03.bc.larksuite.com [209.127.231.36]) by sourceware.org (Postfix) with UTF8SMTPS id D93A33856958 for ; Fri, 5 May 2023 09:41:47 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D93A33856958 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=oss.cipunited.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=oss.cipunited.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=s1; d=oss-cipunited-com.20200927.dkim.feishu.cn; t=1683279702; h=from:subject:mime-version:from:date:message-id:subject:to:cc: reply-to:content-type:mime-version:in-reply-to:message-id; bh=p2xDm8EyewIWJfWez+riz+BGtjpGwjT4QTYlAAo6yec=; b=XNfC/SAZhS5srK1sju3Cn84y4DzMIifBDxtMKylnBeaOzXbVdoPzerL3FUnQAixPRtbXfF 9pXidyoDptMLRWEO2gbX8QFiSR6ieT0GUnPLoj11fEmHmPO+u9sfx3L5uehfkgGxDojEyL LE2TsSvzZqn7DhMBHc7fehxuszN5x5TMziyv1z1T384mIg3EwMhjwGvitKl55Z+VtPkSOy IQoNSno5RauVvT3GFp+Bbfk26M4HpKCj2ZK+JoJ4xYatRQPwY5Jb5+NW3tdfc2ydzMt2Nl QqtD4OpVRVnbm5fUqtM6EQGrjM6aHKMymCINMcf5vW4ySJSFmenRwkZiN5Wo3g== X-Lms-Return-Path: X-Mailer: git-send-email 2.40.1 Date: Fri, 05 May 2023 17:41:31 +0800 Message-Id: Mime-Version: 1.0 To: From: "Jie Mei" Subject: [PATCH 0/8] MIPS: Add MIPS16e2 ASE instrucions. X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, HTML_MESSAGE, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-Content-Filtered-By: Mailman/MimeDel 2.1.29 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765046943304357543?= X-GMAIL-MSGID: =?utf-8?q?1765046943304357543?= The MIPS16e2 ASE is an enhancement to the MIPS16e ASE, which includes all MIPS16e instructions, with some addition. This series of patches adds all instructions of MIPS16E2 ASE. Jie Mei (8): MIPS: Add basic support for mips16e2 MIPS: Add MOVx instructions support for mips16e2 MIPS: Add instruction about global pointer register for mips16e2 MIPS: Add bitwise instructions for mips16e2 MIPS: Add LUI instruction for mips16e2 MIPS: Add load/store word left/right instructions for mips16e2 MIPS: Use ISA_HAS_9BIT_DISPLACEMENT for mips16e2 MIPS: Add CACHE instruction for mips16e2 gcc/config/mips/constraints.md | 4 + gcc/config/mips/mips-protos.h | 4 + gcc/config/mips/mips.cc | 164 ++++++++++-- gcc/config/mips/mips.h | 32 ++- gcc/config/mips/mips.md | 188 ++++++++++++-- gcc/config/mips/mips.opt | 4 + gcc/config/mips/predicates.md | 19 +- gcc/doc/invoke.texi | 7 + gcc/testsuite/gcc.target/mips/mips.exp | 10 + .../gcc.target/mips/mips16e2-cache.c | 34 +++ gcc/testsuite/gcc.target/mips/mips16e2-cmov.c | 68 +++++ gcc/testsuite/gcc.target/mips/mips16e2-gp.c | 101 ++++++++ gcc/testsuite/gcc.target/mips/mips16e2.c | 240 ++++++++++++++++++ 13 files changed, 816 insertions(+), 59 deletions(-) create mode 100644 gcc/testsuite/gcc.target/mips/mips16e2-cache.c create mode 100644 gcc/testsuite/gcc.target/mips/mips16e2-cmov.c create mode 100644 gcc/testsuite/gcc.target/mips/mips16e2-gp.c create mode 100644 gcc/testsuite/gcc.target/mips/mips16e2.c