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bh=QM/+h6e5d3+PytzUsNKu451AySS++fB6lEoycxK6Jtk=; b=OJrXpwPqJZQ1SgFt7eWy9njphGwEfbogad1jm26zQbaEx11gs2Ryt+MI5XtZ2+eB7S tpXBhzXvGwg02XTYBg4Bi7qheO7hjqxeo/ZY45U6Gih12VmGnVNYJXAGNGTHWYfTVaeB 9V+rmsJzFysBVnN/pArOz8QxPLxyttEChajyyAk9OMbrZ0oiboq8rgTRg7Vaaq78fvuG dX8MU+eiGILXS+SkoG+KWbRAStgcSneKHT4RD5/6jXLE1tAYdYtL/fTlm+7zlS5Buxw2 NpgngSSLlDQ9EK+DgEe0PGJN8SzFCtNUga8NsrteL6DA+jGFoFLA0ckwZPbcV/ctq/P2 LmDw== X-Gm-Message-State: AOJu0YzCgZp9HUQl0Vgn4mD49GDfcBs6j8hA5DEq6kghKVfXTOl+Nmyl MROv5tZDn0oCviohPeszes+HTW5pk50+myfGFCQ4+wHy1bg= X-Received: by 2002:a05:600c:4fd5:b0:40d:6f89:a839 with SMTP id o21-20020a05600c4fd500b0040d6f89a839mr4858607wmq.30.1705425245019; Tue, 16 Jan 2024 09:14:05 -0800 (PST) Received: from troughton.lym.embecosm-corp.com ([212.69.42.53]) by smtp.gmail.com with ESMTPSA id o21-20020a05600c4fd500b0040e34ca648bsm20045876wmq.0.2024.01.16.09.14.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jan 2024 09:14:04 -0800 (PST) From: Mary Bennett To: gcc-patches@gcc.gnu.org Cc: mary.bennett@embecosm.com Subject: [PATCH v3 0/2] RISC-V: Support CORE-V XCVSIMD extension Date: Tue, 16 Jan 2024 17:13:49 +0000 Message-Id: <20240116171351.913881-1-mary.bennett@embecosm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240116163529.623568-1-mary.bennett@embecosm.com> References: <20240116163529.623568-1-mary.bennett@embecosm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-5.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782087532751518091 X-GMAIL-MSGID: 1788268058208184836 v2 -> v3: * Removed duplicate ftype. This patch series presents the comprehensive implementation of the SIMD extension for CORE-V. Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to ensure its correctness and compatibility with the existing codebase. However, your input, reviews, and suggestions are invaluable in making this extension even more robust. The CORE-V builtins are described in the specification [1] and work can be found in the OpenHW group's Github repository [2]. [1] github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md [2] github.com/openhwgroup/corev-gcc Contributors: Mary Bennett Nandni Jamnadas Pietra Ferreira Charlie Keaney Jessica Mills Craig Blackmore Simon Cook Jeremy Bennett Helene Chelin RISC-V: Add support for XCVsimd extension in CV32E40P RISC-V: Fix XCValu test gcc/common/config/riscv/riscv-common.cc | 2 + gcc/config/riscv/constraints.md | 30 + gcc/config/riscv/corev.def | 156 ++ gcc/config/riscv/corev.md | 1908 +++++++++++++++++ gcc/config/riscv/predicates.md | 20 + gcc/config/riscv/riscv-builtins.cc | 1 + gcc/config/riscv/riscv-ftypes.def | 8 + gcc/config/riscv/riscv.cc | 8 + gcc/config/riscv/riscv.opt | 2 + gcc/doc/extend.texi | 886 ++++++++ gcc/doc/sourcebuild.texi | 3 + .../gcc.target/riscv/cv-alu-fail-compile.c | 40 +- .../riscv/cv-simd-abs-b-compile-1.c | 11 + .../riscv/cv-simd-abs-h-compile-1.c | 11 + .../riscv/cv-simd-add-b-compile-1.c | 11 + .../riscv/cv-simd-add-div2-compile-1.c | 11 + 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