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bh=VzktpZgNVDy6R5+ailz521La2c9Ssl50aevLgWuDj2U=; b=cj4D80wCrLyhLsOwLLaxh+e1Bhs2695Kcs2XrhIlk++TirEPUUnN3iyyzrF6aI/GXy e1pa4yjU2nCVYjiHp/IEaS3/KU2tPDVYt8KTNnKXaafUoO9KV5V7cM5AlNoQUki6WWrY 1E8VHSviZg4jI+0Z/tqKjWrtlmq/JGypRs44vHA8aQqgsXSs9lFf5WdvikmdR+zpuduS PQJ3iIwpzAOp/wuQ78QHyR1Ya1min9Z8e8v/8GxdkLVkPvnnPLmshoFLSnxYb4LTX+Ex bZMgpsamuvekGcqQjO/O3Oq9/eew3JdVAoCBOoCxbHn6OarmQx8aG2UEVPJQetUu2ydj cSFQ== X-Gm-Message-State: AOJu0YwLYiQoBoSFDYo3PtytLNzT0oYahumNyDhFPOMlZmdJHI5l8Cxa QsG3yB4746fzLFk+fNfuwSpaF0cYTFM57CMjXftpBocoOi0= X-Received: by 2002:a7b:ce97:0:b0:40e:6963:4471 with SMTP id q23-20020a7bce97000000b0040e69634471mr3181205wmj.232.1705422944164; Tue, 16 Jan 2024 08:35:44 -0800 (PST) Received: from troughton.lym.embecosm-corp.com ([212.69.42.53]) by smtp.gmail.com with ESMTPSA id j7-20020a05600c190700b0040e52cac976sm23442096wmq.29.2024.01.16.08.35.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jan 2024 08:35:43 -0800 (PST) From: Mary Bennett To: gcc-patches@gcc.gnu.org Cc: mary.bennett@embecosm.com Subject: [PATCH v2 0/2] RISC-V: Support CORE-V XCVSIMD extension Date: Tue, 16 Jan 2024 16:35:27 +0000 Message-Id: <20240116163529.623568-1-mary.bennett@embecosm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231109115736.541131-1-mary.bennett@embecosm.com> References: <20231109115736.541131-1-mary.bennett@embecosm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-5.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782087532751518091 X-GMAIL-MSGID: 1788265682135191584 This patch series presents the comprehensive implementation of the SIMD extension for CORE-V. Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to ensure its correctness and compatibility with the existing codebase. However, your input, reviews, and suggestions are invaluable in making this extension even more robust. The CORE-V builtins are described in the specification [1] and work can be found in the OpenHW group's Github repository [2]. [1] github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md [2] github.com/openhwgroup/corev-gcc Contributors: Mary Bennett Nandni Jamnadas Pietra Ferreira Charlie Keaney Jessica Mills Craig Blackmore Simon Cook Jeremy Bennett Helene Chelin RISC-V: Add support for XCVsimd extension in CV32E40P RISC-V: Fix XCValu test gcc/common/config/riscv/riscv-common.cc | 2 + gcc/config/riscv/constraints.md | 30 + gcc/config/riscv/corev.def | 156 ++ gcc/config/riscv/corev.md | 1908 +++++++++++++++++ gcc/config/riscv/predicates.md | 20 + gcc/config/riscv/riscv-builtins.cc | 1 + gcc/config/riscv/riscv-ftypes.def | 9 + gcc/config/riscv/riscv.cc | 8 + gcc/config/riscv/riscv.opt | 2 + gcc/doc/extend.texi | 886 ++++++++ gcc/doc/sourcebuild.texi | 3 + .../riscv/cv-simd-abs-b-compile-1.c | 11 + .../riscv/cv-simd-abs-h-compile-1.c | 11 + .../riscv/cv-simd-add-b-compile-1.c | 11 + .../riscv/cv-simd-add-div2-compile-1.c | 11 + .../riscv/cv-simd-add-div4-compile-1.c | 11 + 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