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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id u18-20020a05622a14d200b00420edc802d1si8112546qtx.0.2023.11.15.01.47.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Nov 2023 01:47:41 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=DKAWswzJ; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 6F01C3857835 for ; Wed, 15 Nov 2023 09:47:38 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.31]) by sourceware.org (Postfix) with ESMTPS id 700EA3858C78 for ; Wed, 15 Nov 2023 09:47:12 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 700EA3858C78 Authentication-Results: sourceware.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 700EA3858C78 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=134.134.136.31 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700041634; cv=none; b=vUbkiJClvBInUpZa49tbMdaXpFyC2f6SfiDEFr4ldP3HlC7MoZzvYI1chvPdLbhhHVgxXMW5brCObtDgQX2XExP3hsFm+RRqA5D+1TJv6T2W0dNGL6OKTB0Mr7kke3WkNe5DvLRIT98nZQ0UlRZL01WCJQD6doz5x03cy4HDRz8= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700041634; c=relaxed/simple; bh=E5itHj7FF4eXb3OwP707VzHWr6X4tQbLn/2A+AjGivM=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=GR+rU09Ms4WlrrD26ED2h5lmKWY8fJUeaPAGXngrHQ84VB5qJbC8NQLFcraz0TZDkTjVTDbDLfS9ywF8AnnUtNau596z51fFGbTQBwJicTKeFylLw4HGFRBZ4bXISIoxD+OMCJgNkvmMjtmyZA6gugEEdpdiUHlfr4EtgvSQZqs= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1700041632; x=1731577632; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=E5itHj7FF4eXb3OwP707VzHWr6X4tQbLn/2A+AjGivM=; b=DKAWswzJ473c5SHJ24MvsQtEoT+8zaQm8U1uC4lmC3Tg3rIuKdSTOeJD PCwuGT+TVOzzldokClDjBqEa84XRjbUPa8XXHRDL6ZDskArwZpBvB2u/o cUlfCEDWpaQVtuQ6esR3v3SGPYTY9SuwjjOyEu1U4owIsGrS/O1FHf+Hs 2v4xBQwQHkr5YKlw95Vpm1sRKUf2AcnognE1PLv+vjMTlfs5WBkuTsl52 xK0ny70pZyMgBYIlOHpe6QVhaUF2o9nIzsNsk3LDF0MmhqDz3NWj/G8YU mnlhYMat2NoWLatuMNmutklgIcXJFuQQjdzuQ8s1Pjf5F8j3bmM7ux6eF g==; X-IronPort-AV: E=McAfee;i="6600,9927,10894"; a="455138353" X-IronPort-AV: E=Sophos;i="6.03,304,1694761200"; d="scan'208";a="455138353" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Nov 2023 01:47:09 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.03,304,1694761200"; d="scan'208";a="6105935" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orviesa002.jf.intel.com with ESMTP; 15 Nov 2023 01:47:07 -0800 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id A63491005674; Wed, 15 Nov 2023 17:47:05 +0800 (CST) From: Hongyu Wang To: gcc-patches@gcc.gnu.org Cc: ubizjak@gmail.com, hongtao.liu@intel.com Subject: [PATCH 00/16] Support Intel APX NDD Date: Wed, 15 Nov 2023 17:46:49 +0800 Message-Id: <20231115094705.3976553-1-hongyu.wang@intel.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, KAM_SHORT, SPF_HELO_NONE, SPF_SOFTFAIL, TXREP, T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782622885314285335 X-GMAIL-MSGID: 1782622885314285335 Hi, Intel APX NDD feature has been released in [1]. NDD means New data destination. In such forms, NDD is the new destination register receiving the result of the computation and all other operands (including the original destination operand) become read-only source operands. This feature, i.e. Existing form | Existing semantics | NDD extension | NDD semantics INC r/m | r/m := r/m + 1 | INC ndd, r/m | ndd := r/m + 1 SUB r/m, imm | r/m := r/m - imm | SUB ndd, r/m, imm | ndd(v) := r/m - imm SUB r/m, reg | r/m := r/m - reg | SUB ndd, r/m, reg | ndd(v) := r/m - reg SUB reg, r/m | reg := reg - r/m | SUB ndd, reg, r/m | ndd(v) := reg - r/m Theoratically, it will provide more flexibility in compiler optimization. In this series of patch, we will suport below instructions as basic NDD support: INC, DEC, NOT, NEG, ADD, SUB, ADC, SBB, AND, OR, XOR, SAL, SAR, SHL, SHR, RCL, RCR, ROL, ROR, SHLD, SHRD, CMOVcc In GCC, legacy insns will have constraint "0" to operands[1], so for NDD form we adds extra alternatives like "r, rm, r", and restrict them under NDD only. We also made necessary changes in ix86_fixup_*_operators for binary/unary operations to allow different src and dest. We also added several adjustment to avoid miscompile under NDD alternatives which are explained in each standalone patch (i.e. There are some implicit assumptions in TImode doubleword splitter that operands[0] and operands[1] are the same). This series of patches are basic NDD supports. In the future we will continuously support NDD optimizations. Bootstrapped/regtested on x86-64-pc-linux{-m32,} and SDE, also passed SPEC sde simulation run. Hongyu Wang (7): [APX NDD] Restrict TImode register usage when NDD enabled [APX NDD] Disable seg_prefixed memory usage for NDD add [APX NDD] Support APX NDD for left shift insns [APX NDD] Support APX NDD for right shift insns [APX NDD] Support APX NDD for rotate insns [APX NDD] Support APX NDD for shld/shrd insns [APX NDD] Support APX NDD for cmove insns Kong Lingling (9): [APX NDD] Support Intel APX NDD for legacy add insn [APX NDD] Support APX NDD for optimization patterns of add [APX NDD] Support APX NDD for adc insns [APX NDD] Support APX NDD for sub insns [APX NDD] Support APX NDD for sbb insn [APX NDD] Support APX NDD for neg insn [APX NDD] Support APX NDD for not insn [APX NDD] Support APX NDD for and insn [APX NDD] Support APX NDD for or/xor insn gcc/config/i386/constraints.md | 5 + gcc/config/i386/i386-expand.cc | 51 +- gcc/config/i386/i386-options.cc | 3 + gcc/config/i386/i386-protos.h | 15 +- gcc/config/i386/i386.cc | 40 +- gcc/config/i386/i386.md | 2367 +++++++++++------ gcc/testsuite/gcc.target/i386/apx-ndd-adc.c | 15 + gcc/testsuite/gcc.target/i386/apx-ndd-cmov.c | 16 + gcc/testsuite/gcc.target/i386/apx-ndd-sbb.c | 6 + .../gcc.target/i386/apx-ndd-shld-shrd.c | 24 + gcc/testsuite/gcc.target/i386/apx-ndd.c | 202 ++ .../gcc.target/i386/apx-spill_to_egprs-1.c | 8 +- 12 files changed, 1984 insertions(+), 768 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/apx-ndd-adc.c create mode 100644 gcc/testsuite/gcc.target/i386/apx-ndd-cmov.c create mode 100644 gcc/testsuite/gcc.target/i386/apx-ndd-sbb.c create mode 100644 gcc/testsuite/gcc.target/i386/apx-ndd-shld-shrd.c create mode 100644 gcc/testsuite/gcc.target/i386/apx-ndd.c