mbox series

[00/16] Support Intel APX NDD

Message ID 20231115094705.3976553-1-hongyu.wang@intel.com
Headers
Series Support Intel APX NDD |

Message

Hongyu Wang Nov. 15, 2023, 9:46 a.m. UTC 
  Hi,

Intel APX NDD feature has been released in [1]. 

NDD means New data destination. In such forms, NDD is the new destination
register receiving the result of the computation and all other operands
(including the original destination operand) become read-only source operands.
This feature, i.e.

Existing form | Existing semantics | NDD extension     | NDD semantics
INC r/m       | r/m := r/m + 1 	   | INC ndd, r/m      | ndd := r/m + 1
SUB r/m, imm  | r/m := r/m - imm   | SUB ndd, r/m, imm | ndd(v) := r/m - imm
SUB r/m, reg  | r/m := r/m - reg   | SUB ndd, r/m, reg | ndd(v) := r/m - reg
SUB reg, r/m  | reg := reg - r/m   | SUB ndd, reg, r/m | ndd(v) := reg - r/m

Theoratically, it will provide more flexibility in compiler optimization.

In this series of patch, we will suport below instructions as basic NDD
support:
INC, DEC, NOT, NEG, ADD, SUB, ADC, SBB, AND, OR, XOR, SAL, SAR, SHL, SHR, RCL,
RCR, ROL, ROR, SHLD, SHRD, CMOVcc

In GCC, legacy insns will have constraint "0" to operands[1], so for NDD form
we adds extra alternatives like "r, rm, r", and restrict them under NDD only.
We also made necessary changes in ix86_fixup_*_operators for binary/unary
operations to allow different src and dest. We also added several adjustment
to avoid miscompile under NDD alternatives which are explained in each
standalone patch (i.e. There are some implicit assumptions in TImode
doubleword splitter that operands[0] and operands[1] are the same). 

This series of patches are basic NDD supports. In the future we will
continuously support NDD optimizations.

Bootstrapped/regtested on x86-64-pc-linux{-m32,} and SDE, also passed SPEC sde
simulation run.

Hongyu Wang (7):
  [APX NDD] Restrict TImode register usage when NDD enabled
  [APX NDD] Disable seg_prefixed memory usage for NDD add
  [APX NDD] Support APX NDD for left shift insns
  [APX NDD] Support APX NDD for right shift insns
  [APX NDD] Support APX NDD for rotate insns
  [APX NDD] Support APX NDD for shld/shrd insns
  [APX NDD] Support APX NDD for cmove insns

Kong Lingling (9):
  [APX NDD] Support Intel APX NDD for legacy add insn
  [APX NDD] Support APX NDD for optimization patterns of add
  [APX NDD] Support APX NDD for adc insns
  [APX NDD] Support APX NDD for sub insns
  [APX NDD] Support APX NDD for sbb insn
  [APX NDD] Support APX NDD for neg insn
  [APX NDD] Support APX NDD for not insn
  [APX NDD] Support APX NDD for and insn
  [APX NDD] Support APX NDD for or/xor insn

 gcc/config/i386/constraints.md                |    5 +
 gcc/config/i386/i386-expand.cc                |   51 +-
 gcc/config/i386/i386-options.cc               |    3 +
 gcc/config/i386/i386-protos.h                 |   15 +-
 gcc/config/i386/i386.cc                       |   40 +-
 gcc/config/i386/i386.md                       | 2367 +++++++++++------
 gcc/testsuite/gcc.target/i386/apx-ndd-adc.c   |   15 +
 gcc/testsuite/gcc.target/i386/apx-ndd-cmov.c  |   16 +
 gcc/testsuite/gcc.target/i386/apx-ndd-sbb.c   |    6 +
 .../gcc.target/i386/apx-ndd-shld-shrd.c       |   24 +
 gcc/testsuite/gcc.target/i386/apx-ndd.c       |  202 ++
 .../gcc.target/i386/apx-spill_to_egprs-1.c    |    8 +-
 12 files changed, 1984 insertions(+), 768 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/i386/apx-ndd-adc.c
 create mode 100644 gcc/testsuite/gcc.target/i386/apx-ndd-cmov.c
 create mode 100644 gcc/testsuite/gcc.target/i386/apx-ndd-sbb.c
 create mode 100644 gcc/testsuite/gcc.target/i386/apx-ndd-shld-shrd.c
 create mode 100644 gcc/testsuite/gcc.target/i386/apx-ndd.c