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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id dt12-20020a05620a478c00b0077a3e4cdd5fsi3149250qkb.420.2023.11.12.06.53.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Nov 2023 06:53:01 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 151923858C01 for ; Sun, 12 Nov 2023 14:53:01 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 631943858D20 for ; Sun, 12 Nov 2023 14:52:37 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 631943858D20 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 631943858D20 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699800758; cv=none; b=OKjtKa1yfBuQP42mzNxQ0LQVPLmBfOvNutiLXOl+Q0lR0UPQ1u6rEVovTfxQ1IB4KTODi7yWdUfpKLqMrKXbn7uZWXK39nfDC1ORBMRG/zwB953y9Y4XV8E8HtM5svgFuK/qWgCrDuUPsVvzpWrhNxmdelsWWE9URBHWE2kJOjU= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699800758; c=relaxed/simple; bh=MjE7mGVIvh8YdDKJZtk7YX2LWxXyUnAYdocMoMFVA9s=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=FD3ShRpZj1D2/W5DCQ5JEAZq/kXDC8l5Oxw9FNkjjx/eNw4aQBiczF/chilp3lLnUe444MXbmef9JJzCgLk7LuUNGXJ42NEZPk9i2NmnNX+XVWBs+32JXJAytF19oW6yfGEFRH/8xoXrH9GUWHgT3+FwCuliYzeiVzsAdwv3sMo= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E17B0DA7; Sun, 12 Nov 2023 06:53:21 -0800 (PST) Received: from e121540-lin.manchester.arm.com (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 4046A3F7B4; Sun, 12 Nov 2023 06:52:36 -0800 (PST) From: Richard Sandiford To: jlaw@ventanamicro.com, vmakarov@redhat.com, gcc-patches@gcc.gnu.org Cc: Richard Sandiford Subject: [PATCH 0/5] Add support for operand-specific alignment requirements Date: Sun, 12 Nov 2023 14:52:24 +0000 Message-Id: <20231112145229.2924713-1-richard.sandiford@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-17.3 required=5.0 tests=BAYES_00, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782370303971482788 X-GMAIL-MSGID: 1782370303971482788 SME has various instructions that require aligned register tuples. However, the associated tuple modes are already widely used and do not need to be aligned in other contexts. It therefore isn't appropriate to force alignment in TARGET_HARD_REGNO_MODE_OK. There are also strided loads and stores that require: - (regno & 0x8) == 0 for 2-register tuples - (regno & 0xc) == 0 for 4-register tuples Although the requirements for strided loads and stores could be enforced by C++ conditions on the insn, it's convenient to handle them in the same way as alignment. This series of patches therefore adds a way for register constraints to specify which start registers are valid and which aren't. Most of the details are in the covering note to the first patch. This is clearly changing a performance-sensitive part of the compiler. I've tried to ensure that the overhead is only small for targets that use the new feature. Almost all of the new code gets optimised away on targets that don't use the feature. Richard Sandiford (5): Add register filter operand to define_register_constraint recog: Handle register filters lra: Handle register filters ira: Handle register filters Add an aligned_register_operand predicate gcc/common.md | 28 ++++++++ gcc/doc/md.texi | 41 +++++++++++- gcc/doc/tm.texi | 3 +- gcc/doc/tm.texi.in | 3 +- gcc/genconfig.cc | 2 + gcc/genpreds.cc | 146 ++++++++++++++++++++++++++++++++++++++++- gcc/gensupport.cc | 48 +++++++++++++- gcc/gensupport.h | 3 + gcc/ira-build.cc | 8 +++ gcc/ira-color.cc | 10 +++ gcc/ira-int.h | 14 ++++ gcc/ira-lives.cc | 61 +++++++++++++++++ gcc/lra-constraints.cc | 13 +++- gcc/recog.cc | 14 +++- gcc/recog.h | 24 ++++++- gcc/reginfo.cc | 5 ++ gcc/rtl.def | 6 +- gcc/target-globals.cc | 6 +- gcc/target-globals.h | 3 + 19 files changed, 421 insertions(+), 17 deletions(-)