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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id w21-20020a50d795000000b0053e4d1cbc6esm1147688edi.55.2023.10.20.02.53.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 02:53:51 -0700 (PDT) From: Christoph Muellner To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Palmer Dabbelt , Andrew Waterman , Philipp Tomsich , Jeff Law Cc: =?utf-8?q?Christoph_M=C3=BCllner?= Subject: [PATCH v2 0/2] riscv: Adding support for XTHead(F)MemIdx Date: Fri, 20 Oct 2023 11:53:46 +0200 Message-ID: <20231020095348.2455729-1-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 X-Spam-Status: No, score=-6.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, JMQ_SPF_NEUTRAL, KAM_MANYTO, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780267785386725271 X-GMAIL-MSGID: 1780267785386725271 From: Christoph Müllner This two patches add support for the XTheadMemIdx and XTheadFMemIdx ISA extensions, that support additional addressing modes. The extensions are implemented in a range of T-Head cores (e.g. C906, C910, C920) and are available on the market for quite some time. The ISA spec can be found here: https://github.com/T-head-Semi/thead-extension-spec An initial version of these patches has been sent a while ago. Jeff Law suggested to use INSNs instead of peepholes to let the combiner do the optimization. This is the major change that this patches have seen. Both patches come with their own tests and don't introduce any regressions for RV32 or RV64. Further the patches did not show any issues with SPEC CPU 2017 (base&peak) using multiple combinations of XThead* extensions. The patches have been tested on QEMU and a C920-based machine. Changes in v2: * Convert peepholes to INSNs (let the combiner do the work) * Enable XTheadFMemIdx optimizations only if XTheadMemIdx is available (to address the case when GP regs are used in FP mode (e.g. (reg:DF a2)) * Add a insn_and_split (th_memidx_operand) to address the case when reload splits off the index calculation. Christoph Müllner (2): riscv: thead: Add support for the XTheadMemIdx ISA extension riscv: thead: Add support for the XTheadFMemIdx ISA extension gcc/config/riscv/constraints.md | 26 + gcc/config/riscv/riscv-protos.h | 29 + gcc/config/riscv/riscv.cc | 24 +- gcc/config/riscv/riscv.h | 6 +- gcc/config/riscv/riscv.md | 26 +- gcc/config/riscv/thead.cc | 485 ++++++++++++++ gcc/config/riscv/thead.md | 594 +++++++++++++++++- .../riscv/xtheadfmemidx-index-update.c | 20 + .../xtheadfmemidx-index-xtheadbb-update.c | 20 + .../riscv/xtheadfmemidx-index-xtheadbb.c | 22 + .../gcc.target/riscv/xtheadfmemidx-index.c | 22 + .../riscv/xtheadfmemidx-uindex-update.c | 20 + .../xtheadfmemidx-uindex-xtheadbb-update.c | 20 + .../riscv/xtheadfmemidx-uindex-xtheadbb.c | 24 + .../gcc.target/riscv/xtheadfmemidx-uindex.c | 25 + .../gcc.target/riscv/xtheadmemidx-helpers.h | 152 +++++ .../riscv/xtheadmemidx-index-update.c | 27 + .../xtheadmemidx-index-xtheadbb-update.c | 27 + .../riscv/xtheadmemidx-index-xtheadbb.c | 36 ++ .../gcc.target/riscv/xtheadmemidx-index.c | 36 ++ .../riscv/xtheadmemidx-modify-xtheadbb.c | 74 +++ .../gcc.target/riscv/xtheadmemidx-modify.c | 74 +++ .../riscv/xtheadmemidx-uindex-update.c | 27 + .../xtheadmemidx-uindex-xtheadbb-update.c | 27 + .../riscv/xtheadmemidx-uindex-xtheadbb.c | 44 ++ .../gcc.target/riscv/xtheadmemidx-uindex.c | 44 ++ 26 files changed, 1917 insertions(+), 14 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index-update.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index-xtheadbb-update.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index-xtheadbb.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex-update.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex-xtheadbb-update.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex-xtheadbb.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-helpers.h create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-index-update.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-index-xtheadbb-update.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-index-xtheadbb.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-index.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-modify-xtheadbb.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-modify.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-uindex-update.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-uindex-xtheadbb-update.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-uindex-xtheadbb.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-uindex.c