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[8.43.85.97]) by mx.google.com with ESMTPS id c22-20020ac85a96000000b004197929440asi1148396qtc.304.2023.10.19.01.34.31 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Oct 2023 01:34:32 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 0BAA43853535 for ; Thu, 19 Oct 2023 08:34:26 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbguseast2.qq.com (smtpbguseast2.qq.com [54.204.34.130]) by sourceware.org (Postfix) with ESMTPS id BEF643857B98 for ; Thu, 19 Oct 2023 08:33:41 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org BEF643857B98 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai ARC-Filter: OpenARC Filter v1.0.0 sourceware.org BEF643857B98 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=54.204.34.130 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1697704427; cv=none; b=ku3/iCIS6cGUByTQSHpnA/x0ZtUjPTgNDvvDlKH3IMdo4QFzCr7kjrGqDbmvsYz9ecyOANeJCgbgBhphFeA6ff67BVSdoM4Dzk38MZfcJOpKQ9vo9oqBtCPut5ye7ufrNHn0jfoO6rHdlRIj2eI5z+bXsvHN2TdSVTvi3TdbUXA= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1697704427; c=relaxed/simple; bh=a4WBdVXkfGQLOizAqdTUuKkLhza+JjjptKl/lb+T0eA=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=eL47+AtkqVUnMVIXHqWIvrwvb5J9DN9kXI6+YqEfbAkfswDNaBXXduOALNXHB4cRqEIAkmrqQVI45DFX2MOkLYDbOzwPT49CBD1g+tUSy7Mm7I+dr8T39BBwY2VENI7pyeWSwVPmfPptyEfkGHw6CfZAa3qPVkYs4FHT2kHumOM= ARC-Authentication-Results: i=1; server2.sourceware.org X-QQ-mid: bizesmtp65t1697704415tg6d37p0 Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 19 Oct 2023 16:33:34 +0800 (CST) X-QQ-SSF: 01400000000000C0F000000A0000000 X-QQ-FEAT: CR3LFp2JE4kShIs+dzJ7r5hpv20AgNT+jTTfrbIuttXesLLXHgL5IdMSvY2Zo xLYEPZc0PY3JIHDAcll3Pv48eN0BBtzRKJ2EoPTLThMhz+80wv8PPpG7oEX2eNFMDpve0FW TZ3EeYupwxqxY3+0Hu9gxIIXdwwzcgJTX6e9fHDYFGp7HyHhpNm3RIiThlaJbN78Dycvz+j dEOD/LxJWwgAw55+O6hjXRFmgiamXVFTKpN7FvrP1/y0MO6tluedQaAZkI3iO6jaxr/SkIY myA5ldFqZYbvNybylLH0H2sUSIVL9P0k8pbXe20OJbAxIpWa/PVoyFSjTHc8lutWAIHVaTe eoNnMSYRVWFNaASuoEP5QEJ2hXnKyKyqgHv9bwFnGMHYULHnNo= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 5717009542534373551 From: Lehua Ding To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, rdapp.gcc@gmail.com, palmer@rivosinc.com, jeffreyalaw@gmail.com, lehua.ding@rivai.ai Subject: [PATCH V3 00/11] Refactor and cleanup vsetvl pass Date: Thu, 19 Oct 2023 16:33:22 +0800 Message-Id: <20231019083333.2052340-1-lehua.ding@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz6a-0 X-Spam-Status: No, score=-5.5 required=5.0 tests=BAYES_00, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780172164588010703 X-GMAIL-MSGID: 1780172164588010703 This patch refactors and cleanups the vsetvl pass in order to make the code easier to modify and understand. This patch does several things: 1. Introducing a virtual CFG for vsetvl infos and Phase 1, 2 and 3 only maintain and modify this virtual CFG. Phase 4 performs insertion, modification and deletion of vsetvl insns based on the virtual CFG. The Basic block in the virtual CFG is called vsetvl_block_info and the vsetvl information inside is called vsetvl_info. 2. Combine Phase 1 and 2 into a single Phase 1 and unified the demand system, this Phase only fuse local vsetvl info in forward direction. 3. Refactor Phase 3, change the logic for determining whether to uplift vsetvl info to a pred basic block to a more unified method that there is a vsetvl info in the vsetvl defintion reaching in compatible with it. 4. Place all modification operations to the RTL in Phase 4 and Phase 5. Phase 4 is responsible for inserting, modifying and deleting vsetvl instructions based on fully optimized vsetvl infos. Phase 5 removes the avl operand from the RVV instruction and removes the unused dest operand register from the vsetvl insns. These modifications resulted in some testcases needing to be updated. The reasons for updating are summarized below: 1. more optimized vlmax_back_prop-25.c/vlmax_back_prop-26.c/vlmax_conflict-3.c/ vlmax_conflict-12.c/vsetvl-13.c/vsetvl-23.c/ avl_single-23.c/avl_single-89.c/avl_single-95.c/pr109773-1.c 2. less unnecessary fusion avl_single-46.c/imm_bb_prop-1.c/pr109743-2.c/vsetvl-18.c 3. local fuse direction (backward -> forward) scalar_move-1.c/ 4. add some bugfix testcases. pr111037-3.c/pr111037-4.c avl_single-89.c PR target/111037 PR target/111234 PR target/111725 Lehua Ding (11): RISC-V: P1: Refactor avl_info/vl_vtype_info/vector_insn_info/vector_block_info RISC-V: P2: Refactor and cleanup demand system RISC-V: P3: Refactor vector_infos_manager RISC-V: P4: move method from pass_vsetvl to pre_vsetvl RISC-V: P5: combine phase 1 and 2 RISC-V: P6: Add computing reaching definition data flow RISC-V: P7: Move earliest fuse and lcm code to pre_vsetvl class RISC-V: P8: Refactor emit-vsetvl phase and delete post optimization RISC-V: P9: Cleanup and reorganize helper functions RISC-V: P10: Delete riscv-vsetvl.h and adjust riscv-vsetvl.def RISC-V: P11: Adjust and add testcases gcc/config/riscv/riscv-vsetvl.cc | 6502 +++++++---------- gcc/config/riscv/riscv-vsetvl.def | 641 +- gcc/config/riscv/riscv-vsetvl.h | 488 -- gcc/config/riscv/t-riscv | 2 +- .../gcc.target/riscv/rvv/base/scalar_move-1.c | 2 +- .../riscv/rvv/vsetvl/avl_single-104.c | 35 + .../riscv/rvv/vsetvl/avl_single-105.c | 23 + .../riscv/rvv/vsetvl/avl_single-106.c | 34 + .../riscv/rvv/vsetvl/avl_single-107.c | 41 + .../riscv/rvv/vsetvl/avl_single-108.c | 41 + .../riscv/rvv/vsetvl/avl_single-109.c | 45 + .../riscv/rvv/vsetvl/avl_single-23.c | 7 +- .../riscv/rvv/vsetvl/avl_single-46.c | 3 +- .../riscv/rvv/vsetvl/avl_single-84.c | 5 +- .../riscv/rvv/vsetvl/avl_single-89.c | 8 +- .../riscv/rvv/vsetvl/avl_single-95.c | 2 +- .../riscv/rvv/vsetvl/imm_bb_prop-1.c | 7 +- .../gcc.target/riscv/rvv/vsetvl/pr109743-2.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/pr109773-1.c | 2 +- .../riscv/rvv/{base => vsetvl}/pr111037-1.c | 0 .../riscv/rvv/{base => vsetvl}/pr111037-2.c | 0 .../gcc.target/riscv/rvv/vsetvl/pr111037-3.c | 16 + .../gcc.target/riscv/rvv/vsetvl/pr111037-4.c | 16 + .../riscv/rvv/vsetvl/vlmax_back_prop-25.c | 10 +- .../riscv/rvv/vsetvl/vlmax_back_prop-26.c | 10 +- .../riscv/rvv/vsetvl/vlmax_conflict-12.c | 1 - .../riscv/rvv/vsetvl/vlmax_conflict-3.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-13.c | 4 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-18.c | 4 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-23.c | 2 +- 30 files changed, 3263 insertions(+), 4692 deletions(-) delete mode 100644 gcc/config/riscv/riscv-vsetvl.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-104.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-105.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-106.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-108.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-109.c rename gcc/testsuite/gcc.target/riscv/rvv/{base => vsetvl}/pr111037-1.c (100%) rename gcc/testsuite/gcc.target/riscv/rvv/{base => vsetvl}/pr111037-2.c (100%) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-4.c Tested-by: Patrick O'Neill