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Wed, 18 Oct 2023 15:04:15 +0000 From: Victor Do Nascimento To: CC: , , , Victor Do Nascimento Subject: [PATCH V2 0/7] aarch64: Add support for __arm_rsr and __arm_wsr ACLE function family Date: Wed, 18 Oct 2023 16:02:41 +0100 Message-ID: <20231018150310.253793-1-victor.donascimento@arm.com> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: AM7EUR03FT037:EE_|VE1PR08MB5742:EE_|AM7EUR03FT015:EE_|GV1PR08MB8404:EE_ X-MS-Office365-Filtering-Correlation-Id: 89d4db2d-74d9-46a3-accc-08dbcfeb84fd x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: dlBdq7x2Sh5LBafgBv6OeV+5EeEA2lDrXG38VBQfwdI2UL3TTFbmdpwprDv78jUEDECc+7BDdYD84QLGf9Qpob035mbXbzeGba4/HSse4PWllHMo4Sc7d8WZXdX2Q9RXV1u6pK5aZtDQ3CUA4vYjPm8ja/DTb2ww6qZksLpTMoQVSWSkQ203ua4ZvN93qjikLk+j6RLr3fN4KagG14EUPAQ5tF3gNmX4dA0oHEEjP+2G1XGp7A3dR7TOD7ppML9wIGT2Wvh/UmmbyhJ3QffJPx0qr4RT5w3irxkknqT9AhWwuFY89UG6CdwbrN8wFpxEL1kFa/ZmR1ztHIl1+sxyNEPaYMP5BqmQZe43E35/FGlf7G948xWO2whcvoh0PGYIxj3Q8McqhE0j/CL8MANQUFF9Jr8qZzecyEdBQsx3TmxntO5ALMXS7tY71s4mPqRymEa6sGpMX8qH3ueLokGLKCv+E2THLVJk9f0NCX4hYE1UVRkijw7fkf6W76iDcZBpe2+Z7X1+imrL2M+Ld+tf+RBWti2R+yZ36BBPdI4hffLZhUN0oALqNSkjYd9iiMAhBKyynlS0MfjzG3q+++u0NfmCy0wXtth/Uq5f5cTHft7JQ/Lo1ZfTdsNVQZPV1Q6y+0bv2FXkmqRj6KO7a+nnMBgYmWqyam03H0AlnrH26IAXex7MWyVT2VT6xEgWlZUOrRAXQskpr2cpBi0BqrliF3FvAxTpNQKn/H4ViVHk13Q= X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234; 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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM7EUR03FT015.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV1PR08MB8404 X-Spam-Status: No, score=-6.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, KAM_DMARC_NONE, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, UNPARSEABLE_RELAY autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780106151016811651 X-GMAIL-MSGID: 1780106151016811651 This revision of the patch series addresses the following key pieces of upstream feedback: * `aarch64-sys-regs.def', being identical in content to the file with the same name in Binutils, now retains the copyright header from Binutils. * We migrate away from the binary search handling of system-register lookups in favour of a hashmap approach, relaxing the requirement that all entries in `aarch64-sys-reg.def' be kept in alphabetical order. * A static selftest is added for sanity-checking of the contents of `aarch64-sys-regs.def'. Given the move to a hashmap lookup mechanism, no testing is needed for the preservation of alphabetical order, but a test is added to detect spurious duplicate register definitions. --- This patch series adds support for reading and writing to and from system registers via the relevant ACLE-defined builtins [1]. The patch series makes a series of additions to the aarch64-specific areas of the compiler to make this possible. Firstly, a mechanism for defining system registers is established via a new .def file and the new SYSREG macro. This macro is the same as is used in Binutils and system register entries are compatible with either code-base. Given the information contained in this system register definition file, a compile-time validation mechanism is implemented, such that any system register name passed as a string literal argument to these builtins can be checked against known system registers and its use for a given target architecture validated. Finally, patterns for each of these builtins are added to the back-end such that, if all validation criteria are met, the correct assembly is emitted. Thus, the following example of system register access is now valid for GCC: long long old = __arm_rsr("trcseqstr"); __arm_wsr("trcseqstr", new); Testing: - Bootstrap/regtest on aarch64-linux-gnu done. [1] https://arm-software.github.io/acle/main/acle.html Victor Do Nascimento (7): aarch64: Sync system register information with Binutils aarch64: Add support for aarch64-sys-regs.def aarch64: Implement system register validation tools aarch64: Add basic target_print_operand support for CONST_STRING aarch64: Implement system register r/w arm ACLE intrinsic functions aarch64: Add front-end argument type checking for target builtins aarch64: Add system register duplication check selftest gcc/config/aarch64/aarch64-builtins.cc | 233 ++++ gcc/config/aarch64/aarch64-c.cc | 4 +- gcc/config/aarch64/aarch64-protos.h | 5 + gcc/config/aarch64/aarch64-sys-regs.def | 1064 +++++++++++++++++ gcc/config/aarch64/aarch64.cc | 243 ++++ gcc/config/aarch64/aarch64.h | 36 + gcc/config/aarch64/aarch64.md | 17 + gcc/config/aarch64/arm_acle.h | 30 + gcc/config/aarch64/predicates.md | 4 + .../gcc.target/aarch64/acle/rwsr-1.c | 20 + .../gcc.target/aarch64/acle/rwsr-2.c | 15 + gcc/testsuite/gcc.target/aarch64/acle/rwsr.c | 144 +++ 12 files changed, 1813 insertions(+), 2 deletions(-) create mode 100644 gcc/config/aarch64/aarch64-sys-regs.def create mode 100644 gcc/testsuite/gcc.target/aarch64/acle/rwsr-1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/acle/rwsr-2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/acle/rwsr.c