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[8.43.85.97]) by mx.google.com with ESMTPS id j17-20020a170906051100b00997ba1c6f3dsi3363872eja.403.2023.09.22.03.57.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Sep 2023 03:57:38 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="BGJ5Q4/B"; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id AA0C6385F015 for ; Fri, 22 Sep 2023 10:57:03 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.120]) by sourceware.org (Postfix) with ESMTPS id AC6B03858D28 for ; Fri, 22 Sep 2023 10:56:36 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org AC6B03858D28 Authentication-Results: sourceware.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=gmail.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695380196; x=1726916196; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=pdaVr2/O2eUOhcpgCQK8W46RdF4Jia7ZrpMMxjtIEsQ=; b=BGJ5Q4/BgBl+3/l1mUUTb3l9cNxdEMsP/1XFV6qIUJ2QsTONg9nVof37 O3KxgnZL43RZBN5AMkBmvEhuKJ8fGkdJ5osYgElAFzmngTuGb7w428oRc 4XryAcGWY5XCy5nL1gHDkIOqTo1a6R+5/26Y/+rtk1YVzSK1u3j2woWBo noazkU61+F7GTGCwyNYJPPM65acFI3qV6E42I4M+lrANs5XSabYR5IkO6 82WCY4kSKGq1ubNCdT6P7CDxXR0rA4JYHWYKGaUukfHE00S5H38pu4hbj Nrj2PC+ik71LrRpbFtP6s4VA0Zs7rQbnxr7I0QGenb7MjO+0uH0gds+Eh Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10840"; a="379680780" X-IronPort-AV: E=Sophos;i="6.03,167,1694761200"; d="scan'208";a="379680780" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Sep 2023 03:56:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10840"; a="782615853" X-IronPort-AV: E=Sophos;i="6.03,167,1694761200"; d="scan'208";a="782615853" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga001.jf.intel.com with ESMTP; 22 Sep 2023 03:56:32 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 9E3951005134; Fri, 22 Sep 2023 18:56:31 +0800 (CST) From: Hongyu Wang To: gcc-patches@gcc.gnu.org Cc: ubizjak@gmail.com, vmakarov@redhat.com, jakub@redhat.com Subject: [PATCH v2 00/13] Support Intel APX EGPR Date: Fri, 22 Sep 2023 18:56:18 +0800 Message-Id: <20230922105631.2298849-1-hongyu.wang@intel.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, KAM_SHORT, SPF_HELO_NONE, SPF_SOFTFAIL, TXREP autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777735050117813167 X-GMAIL-MSGID: 1777735050117813167 Hi, This is a v2 patch for APX support which follows-up previous discussion in https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628904.html As discussed in previous thread, the inverse approach to extend base/index reg support with new memory constraints requrires much more effort both in middle-end and backend, so we keep the backend implementation logic. Also for inline asm, it is hard to provide memory constraint to use EGPR by force due to the limitation of base/index reg class hook, so we just add one register class that allows EGPR usage by force. The major changes are 1. Add new macros INSN_BASE_REG_CLASS/REGNO_OK_FOR_INSN_BASE_P instead of using old MODE_CODE macros. 2. Add a series of constraints that prohibits EGPR as counterparts of common constraints that may involve register/memory/address. All those are prefixed with "j" to avoid confilts with previous constraints. 3. Support constraint mapping for all gpr related common constraints in inline asm. Bootstrapped/regtested x86_64-linux-gnu. Ok for trunk? Hongyu Wang (2): [APX EGPR] middle-end: Add index_reg_class with insn argument. [APX EGPR] Handle GPR16 only vector move insns Kong Lingling (11): [APX EGPR] middle-end: Add insn argument to base_reg_class [APX_EGPR] Initial support for APX_F [APX EGPR] Add 16 new integer general purpose registers [APX EGPR] Add register and memory constraints that disallow EGPR [APX EGPR] Add backend hook for base_reg_class/index_reg_class. [APX EGPR] Map reg/mem constraints in inline asm to non-EGPR constraint. [APX EGPR] Handle legacy insn that only support GPR16 (1/5) [APX EGPR] Handle legacy insns that only support GPR16 (2/5) [APX EGPR] Handle legacy insns that only support GPR16 (3/5) [APX_EGPR] Handle legacy insns that only support GPR16 (4/5) [APX EGPR] Handle vex insns that only support GPR16 (5/5) gcc/addresses.h | 29 +- gcc/common/config/i386/cpuinfo.h | 12 +- gcc/common/config/i386/i386-common.cc | 17 + gcc/common/config/i386/i386-cpuinfo.h | 1 + gcc/common/config/i386/i386-isas.h | 1 + gcc/config/i386/constraints.md | 65 +- gcc/config/i386/cpuid.h | 1 + gcc/config/i386/i386-isa.def | 1 + gcc/config/i386/i386-options.cc | 18 + gcc/config/i386/i386-opts.h | 8 + gcc/config/i386/i386-protos.h | 5 + gcc/config/i386/i386.cc | 303 ++++++- gcc/config/i386/i386.h | 69 +- gcc/config/i386/i386.md | 131 ++- gcc/config/i386/i386.opt | 30 + gcc/config/i386/mmx.md | 154 ++-- gcc/config/i386/sse.md | 792 ++++++++++++------ gcc/doc/invoke.texi | 11 +- gcc/doc/tm.texi | 21 + gcc/doc/tm.texi.in | 21 + gcc/lra-constraints.cc | 32 +- gcc/reload.cc | 34 +- gcc/reload1.cc | 2 +- gcc/testsuite/gcc.target/i386/apx-1.c | 8 + .../gcc.target/i386/apx-egprs-names.c | 17 + .../gcc.target/i386/apx-inline-gpr-norex2.c | 25 + .../gcc.target/i386/apx-interrupt-1.c | 102 +++ .../i386/apx-legacy-insn-check-norex2-asm.c | 5 + .../i386/apx-legacy-insn-check-norex2.c | 181 ++++ .../gcc.target/i386/apx-spill_to_egprs-1.c | 25 + gcc/testsuite/lib/target-supports.exp | 10 + 31 files changed, 1683 insertions(+), 448 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/apx-1.c create mode 100644 gcc/testsuite/gcc.target/i386/apx-egprs-names.c create mode 100644 gcc/testsuite/gcc.target/i386/apx-inline-gpr-norex2.c create mode 100644 gcc/testsuite/gcc.target/i386/apx-interrupt-1.c create mode 100644 gcc/testsuite/gcc.target/i386/apx-legacy-insn-check-norex2-asm.c create mode 100644 gcc/testsuite/gcc.target/i386/apx-legacy-insn-check-norex2.c create mode 100644 gcc/testsuite/gcc.target/i386/apx-spill_to_egprs-1.c