From patchwork Wed Sep 13 03:31:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: chenxiaolong X-Patchwork-Id: 13891 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9ecd:0:b0:3f2:4152:657d with SMTP id t13csp830814vqx; Tue, 12 Sep 2023 20:36:01 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGjTP0wsMH6o5jkXCDDjTstbXv9PVB16eQ5YIJekkbtbSeZE7hIPer7SUzZVrUuV1L9XzA7 X-Received: by 2002:aa7:cf03:0:b0:52f:a80b:83c9 with SMTP id a3-20020aa7cf03000000b0052fa80b83c9mr1154783edy.31.1694576161031; Tue, 12 Sep 2023 20:36:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1694576161; cv=none; d=google.com; s=arc-20160816; b=dSipcu4/XxLttBDTmVK7mR4v/RLiPYGokTFrmOgnoO8/7NZhzwajBkyCK2pFcaZ7wW hdhJjN913gVYs91H3FgdVjkO5C4gMnhm/86WdpXGLS1JqAiQWZ8HKLnZ/07ziQcyU2rh tg6tREAiO+nsYJIhqRRZ/2to0oj1oweQUHViIrkIaaD73jjIDWWqLfC4vfP+qDHxYAy1 8cqQDXR5sEu+zkHrvhvR7z2kj3qBh68I+1xnu73WCHIPlO5nwvbnpzORN3JzUBMB0GTf jxDXgpypaEt1h2n3GgsLaFl40o4r2IRqSQaeN7Ja3CUpwEMLQKN70POhRwSVLhfmHb6o ysYg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:message-id:date:subject:cc:to:from:dmarc-filter :delivered-to; bh=tNFS7/+WgHRyZN0bV20zp7pKtrdXYHnN+4DU7hHMtnA=; fh=3pFUYcpS/27XRzOf17GfR86AuNQu+P1CET04YURgCLs=; b=lhnnWz6ZOdOIC/7sSC2r5a8HS7P+DdOJZVLp/ngjUjpbJMSwhhJGAyY4gu8d0ubI4X 2/rpWLuro5X7tgJ2BjZ8zmcjEXjUjncr1ASU4mF76oNmlb4hnWJDlQDQ9uwdYkypq25y e0vDRHy7obUKdFCYrpm5JIeAL6LzKoiq9vwYjjFszO8124unE9ee5U/QqGQNC7NxtKBj WSwp4I3uUT2lphIX/Vo6/eY+0Muyc5+sVNWIx0RTDvA1yF0idvZR/JZbeuxYgtgNFajf WYss4eC8/EDPx9ClaxGMfsA6MpK3n+7SyIP1KkqS4UNHi59SxbXeTmNqBhkrgcmfudnh 9Auw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id w13-20020aa7d28d000000b0052888f9cdbdsi10121047edq.326.2023.09.12.20.36.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Sep 2023 20:36:01 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 577DB3865460 for ; Wed, 13 Sep 2023 03:33:18 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from eggs.gnu.org (eggs.gnu.org [IPv6:2001:470:142:3::10]) by sourceware.org (Postfix) with ESMTPS id 2B6223858024 for ; Wed, 13 Sep 2023 03:32:13 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 2B6223858024 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=loongson.cn Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qgGbm-0000xe-H8 for gcc-patches@gcc.gnu.org; Tue, 12 Sep 2023 23:32:12 -0400 Received: from loongson.cn (unknown [10.10.130.252]) by gateway (Coremail) with SMTP id _____8BxyeorLQFlJDAmAA--.64685S3; Wed, 13 Sep 2023 11:31:56 +0800 (CST) Received: from slurm-master.loongson.cn (unknown [10.10.130.252]) by localhost.localdomain (Coremail) with SMTP id AQAAf8BxrdwqLQFlxQ4CAA--.3491S4; Wed, 13 Sep 2023 11:31:54 +0800 (CST) From: Xiaolong Chen To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, i@xen0n.name, xuchenghua@loongson.cn, chenglulu@loongson.cn, Xiaolong Chen Subject: [PATCH v4 00/23] Add tests for SX vector instructions. Date: Wed, 13 Sep 2023 11:31:25 +0800 Message-Id: <20230913033148.5752-1-chenxiaolong@loongson.cn> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-CM-TRANSID: AQAAf8BxrdwqLQFlxQ4CAA--.3491S4 X-CM-SenderInfo: hfkh05xldrz0tqj6z05rqj20fqof0/1tbiAQANBWUBHCIA5gAAs1 X-Coremail-Antispam: 1Uk129KBj9fXoWfuryxZw15Xw1DKryDAFW7ZFc_yoW5CFyrWo WkAF15Kw17Gr4S9ryUKrn3Xry8GwnakrsY9a9rurn8Grs8Cr1jvF9Fkw1jvry3ZrsxXFy5 WryqkFWDJrZIv3srl-sFpf9Il3svdjkaLaAFLSUrUUUUjb8apTn2vfkv8UJUUUU8wcxFpf 9Il3svdxBIdaVrn0xqx4xG64xvF2IEw4CE5I8CrVC2j2Jv73VFW2AGmfu7bjvjm3AaLaJ3 UjIYCTnIWjp_UUUY17kC6x804xWl14x267AKxVWUJVW8JwAFc2x0x2IEx4CE42xK8VAvwI 8IcIk0rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xG Y2AK021l84ACjcxK6xIIjxv20xvE14v26r1I6r4UM28EF7xvwVC0I7IYx2IY6xkF7I0E14 v26r4j6F4UM28EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAF wI0_Gr1j6F4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc804VCY07AIYIkI8VC2zVCFFI 0UMc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2IY67AKxVWUGVWUXwAv7VC2z280 aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JMxAIw28Icx kI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2Iq xVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwIxGrwCI42 IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8JwCI42IY 6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aV CY1x0267AKxVWUJVW8JbIYCTnIWIevJa73UjIFyTuYvjxUrNtxDUUUU Received-SPF: pass client-ip=114.242.206.163; envelope-from=chenxiaolong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, KAM_DMARC_STATUS, KAM_SHORT, SPF_FAIL, SPF_HELO_PASS, TXREP autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1776891892590629659 X-GMAIL-MSGID: 1776891892590629659 v3 -> v4: Modify the name of the patch file. In order to better test the function of the vector instruction, the 128 bit test cases are further split according to the function of the instruction. Xiaolong Chen (23): LoongArch: Add tests of -mstrict-align option. LoongArch: Add testsuite framework for Loongson SX/ASX. LoongArch: Add tests for Loongson SX builtin functions. LoongArch: Add tests for SX vector floating-point instructions. LoongArch: Add tests for SX vector addition instructions. LoongArch: Add tests for SX vector subtraction instructions. LoongArch: Add tests for SX vector addition vsadd instructions. LoongArch: Add tests for the SX vector multiplication instruction. LoongArch: Add tests for SX vector vavg/vavgr instructions. LoongArch: Add tests for SX vector vmax/vmaxi/vmin/vmini instructions. LoongArch: Add tests for SX vector vexth/vextl/vldi/vneg/vsat instructions. LoongArch: Add tests for SX vector vabsd/vmskgez/vmskltz/vmsknz/vsigncov instructions. LoongArch: Add tests for SX vector vdiv/vmod instructions. LoongArch: Add tests for SX vector vsll/vslli/vsrl/vsrli/vsrln/vsrlni/vsrlr /vsrlri/vslrlrn/vsrlrni instructions. LoongArch: Add tests for SX vector vrotr/vrotri/vsra/vsrai/vsran/vsrani /vsrarn/vsrarni instructions. LoongArch: Add tests for SX vector vssran/vssrani/vssrarn/vssrarni/vssrln /vssrlni/vssrlrn/vssrlrni instructions. LoongArch: Add tests for SX vector vbitclr/vbitclri/vbitrev/vbitrevi/ vbitsel/vbitseli/vbitset/vbitseti/vclo/vclz/vpcnt instructions. LoongArch: Add tests for SX vector floating point arithmetic instructions. LoongArch: Add tests for SX vector vfrstp/vfrstpi/vseq/vseqi/vsle /vslei/vslt/vslti instructions. LoongArch: Add tests for SX vector vfcmp instructions. LoongArch: Add tests for SX vector handling and shuffle instructions. LoongArch: Add tests for SX vector vand/vandi/vandn/vor/vori/vnor/ vnori/vxor/vxori instructions. LoongArch: Add tests for SX vector vfmadd/vfnmadd/vld/vst instructions. .../gcc.target/loongarch/strict-align.c | 12 + .../loongarch/vector/loongarch-vector.exp | 42 + .../loongarch/vector/lsx/lsx-builtin.c | 1461 +++++++++++++++++ .../loongarch/vector/lsx/lsx-vabsd-1.c | 272 +++ .../loongarch/vector/lsx/lsx-vabsd-2.c | 398 +++++ .../loongarch/vector/lsx/lsx-vadd.c | 416 +++++ .../loongarch/vector/lsx/lsx-vadda.c | 344 ++++ .../loongarch/vector/lsx/lsx-vaddi.c | 251 +++ .../loongarch/vector/lsx/lsx-vaddwev-1.c | 335 ++++ .../loongarch/vector/lsx/lsx-vaddwev-2.c | 344 ++++ .../loongarch/vector/lsx/lsx-vaddwev-3.c | 425 +++++ .../loongarch/vector/lsx/lsx-vaddwod-1.c | 408 +++++ .../loongarch/vector/lsx/lsx-vaddwod-2.c | 344 ++++ .../loongarch/vector/lsx/lsx-vaddwod-3.c | 237 +++ .../loongarch/vector/lsx/lsx-vand.c | 159 ++ .../loongarch/vector/lsx/lsx-vandi.c | 67 + .../loongarch/vector/lsx/lsx-vandn.c | 129 ++ .../loongarch/vector/lsx/lsx-vavg-1.c | 398 +++++ .../loongarch/vector/lsx/lsx-vavg-2.c | 308 ++++ .../loongarch/vector/lsx/lsx-vavgr-1.c | 299 ++++ .../loongarch/vector/lsx/lsx-vavgr-2.c | 317 ++++ .../loongarch/vector/lsx/lsx-vbitclr.c | 461 ++++++ .../loongarch/vector/lsx/lsx-vbitclri.c | 279 ++++ .../loongarch/vector/lsx/lsx-vbitrev.c | 407 +++++ .../loongarch/vector/lsx/lsx-vbitrevi.c | 336 ++++ .../loongarch/vector/lsx/lsx-vbitsel.c | 109 ++ .../loongarch/vector/lsx/lsx-vbitseli.c | 84 + .../loongarch/vector/lsx/lsx-vbitset.c | 371 +++++ .../loongarch/vector/lsx/lsx-vbitseti.c | 279 ++++ .../loongarch/vector/lsx/lsx-vbsll.c | 83 + .../loongarch/vector/lsx/lsx-vbsrl.c | 55 + .../loongarch/vector/lsx/lsx-vclo.c | 266 +++ .../loongarch/vector/lsx/lsx-vclz.c | 265 +++ .../loongarch/vector/lsx/lsx-vdiv-1.c | 299 ++++ .../loongarch/vector/lsx/lsx-vdiv-2.c | 254 +++ .../loongarch/vector/lsx/lsx-vexth-1.c | 342 ++++ .../loongarch/vector/lsx/lsx-vexth-2.c | 182 ++ .../loongarch/vector/lsx/lsx-vextl-1.c | 83 + .../loongarch/vector/lsx/lsx-vextl-2.c | 83 + .../loongarch/vector/lsx/lsx-vextrins.c | 479 ++++++ .../loongarch/vector/lsx/lsx-vfadd_d.c | 407 +++++ .../loongarch/vector/lsx/lsx-vfadd_s.c | 470 ++++++ .../loongarch/vector/lsx/lsx-vfclass_d.c | 83 + .../loongarch/vector/lsx/lsx-vfclass_s.c | 74 + .../loongarch/vector/lsx/lsx-vfcmp_caf.c | 244 +++ .../loongarch/vector/lsx/lsx-vfcmp_ceq.c | 516 ++++++ .../loongarch/vector/lsx/lsx-vfcmp_cle.c | 530 ++++++ .../loongarch/vector/lsx/lsx-vfcmp_clt.c | 476 ++++++ .../loongarch/vector/lsx/lsx-vfcmp_cne.c | 378 +++++ .../loongarch/vector/lsx/lsx-vfcmp_cor.c | 170 ++ .../loongarch/vector/lsx/lsx-vfcmp_cun.c | 253 +++ .../loongarch/vector/lsx/lsx-vfcmp_saf.c | 214 +++ .../loongarch/vector/lsx/lsx-vfcmp_seq.c | 450 +++++ .../loongarch/vector/lsx/lsx-vfcmp_sle.c | 407 +++++ .../loongarch/vector/lsx/lsx-vfcmp_slt.c | 512 ++++++ .../loongarch/vector/lsx/lsx-vfcmp_sne.c | 398 +++++ .../loongarch/vector/lsx/lsx-vfcmp_sor.c | 269 +++ .../loongarch/vector/lsx/lsx-vfcmp_sun.c | 335 ++++ .../loongarch/vector/lsx/lsx-vfcvt-1.c | 398 +++++ .../loongarch/vector/lsx/lsx-vfcvt-2.c | 278 ++++ .../loongarch/vector/lsx/lsx-vffint-1.c | 161 ++ .../loongarch/vector/lsx/lsx-vffint-2.c | 264 +++ .../loongarch/vector/lsx/lsx-vffint-3.c | 102 ++ .../loongarch/vector/lsx/lsx-vflogb_d.c | 76 + .../loongarch/vector/lsx/lsx-vflogb_s.c | 185 +++ .../loongarch/vector/lsx/lsx-vfmadd_d.c | 251 +++ .../loongarch/vector/lsx/lsx-vfmadd_s.c | 381 +++++ .../loongarch/vector/lsx/lsx-vfmax_d.c | 200 +++ .../loongarch/vector/lsx/lsx-vfmax_s.c | 335 ++++ .../loongarch/vector/lsx/lsx-vfmaxa_d.c | 155 ++ .../loongarch/vector/lsx/lsx-vfmaxa_s.c | 230 +++ .../loongarch/vector/lsx/lsx-vfnmadd_d.c | 196 +++ .../loongarch/vector/lsx/lsx-vfnmadd_s.c | 381 +++++ .../loongarch/vector/lsx/lsx-vfrint_d.c | 230 +++ .../loongarch/vector/lsx/lsx-vfrint_s.c | 350 ++++ .../loongarch/vector/lsx/lsx-vfrstp.c | 218 +++ .../loongarch/vector/lsx/lsx-vfrstpi.c | 209 +++ .../loongarch/vector/lsx/lsx-vfsqrt_d.c | 216 +++ .../loongarch/vector/lsx/lsx-vfsqrt_s.c | 372 +++++ .../loongarch/vector/lsx/lsx-vftint-1.c | 349 ++++ .../loongarch/vector/lsx/lsx-vftint-2.c | 695 ++++++++ .../loongarch/vector/lsx/lsx-vftint-3.c | 1028 ++++++++++++ .../loongarch/vector/lsx/lsx-vftint-4.c | 345 ++++ .../loongarch/vector/lsx/lsx-vhaddw-1.c | 488 ++++++ .../loongarch/vector/lsx/lsx-vhaddw-2.c | 452 +++++ .../loongarch/vector/lsx/lsx-vhsubw-1.c | 327 ++++ .../loongarch/vector/lsx/lsx-vhsubw-2.c | 353 ++++ .../loongarch/vector/lsx/lsx-vilvh.c | 353 ++++ .../loongarch/vector/lsx/lsx-vilvl.c | 327 ++++ .../loongarch/vector/lsx/lsx-vinsgr2vr.c | 278 ++++ .../gcc.target/loongarch/vector/lsx/lsx-vld.c | 62 + .../loongarch/vector/lsx/lsx-vldi.c | 61 + .../loongarch/vector/lsx/lsx-vmadd.c | 450 +++++ .../loongarch/vector/lsx/lsx-vmaddwev-1.c | 472 ++++++ .../loongarch/vector/lsx/lsx-vmaddwev-2.c | 383 +++++ .../loongarch/vector/lsx/lsx-vmaddwev-3.c | 383 +++++ .../loongarch/vector/lsx/lsx-vmaddwod-1.c | 372 +++++ .../loongarch/vector/lsx/lsx-vmaddwod-2.c | 438 +++++ .../loongarch/vector/lsx/lsx-vmaddwod-3.c | 460 ++++++ .../loongarch/vector/lsx/lsx-vmax-1.c | 317 ++++ .../loongarch/vector/lsx/lsx-vmax-2.c | 362 ++++ .../loongarch/vector/lsx/lsx-vmaxi-1.c | 279 ++++ .../loongarch/vector/lsx/lsx-vmaxi-2.c | 223 +++ .../loongarch/vector/lsx/lsx-vmin-1.c | 434 +++++ .../loongarch/vector/lsx/lsx-vmin-2.c | 344 ++++ .../loongarch/vector/lsx/lsx-vmini-1.c | 314 ++++ .../loongarch/vector/lsx/lsx-vmini-2.c | 216 +++ .../loongarch/vector/lsx/lsx-vmod-1.c | 254 +++ .../loongarch/vector/lsx/lsx-vmod-2.c | 254 +++ .../loongarch/vector/lsx/lsx-vmskgez.c | 119 ++ .../loongarch/vector/lsx/lsx-vmskltz.c | 321 ++++ .../loongarch/vector/lsx/lsx-vmsknz.c | 104 ++ .../loongarch/vector/lsx/lsx-vmsub.c | 461 ++++++ .../loongarch/vector/lsx/lsx-vmuh-1.c | 353 ++++ .../loongarch/vector/lsx/lsx-vmuh-2.c | 372 +++++ .../loongarch/vector/lsx/lsx-vmul.c | 282 ++++ .../loongarch/vector/lsx/lsx-vmulwev-1.c | 434 +++++ .../loongarch/vector/lsx/lsx-vmulwev-2.c | 344 ++++ .../loongarch/vector/lsx/lsx-vmulwev-3.c | 245 +++ .../loongarch/vector/lsx/lsx-vmulwod-1.c | 272 +++ .../loongarch/vector/lsx/lsx-vmulwod-2.c | 282 ++++ .../loongarch/vector/lsx/lsx-vmulwod-3.c | 308 ++++ .../loongarch/vector/lsx/lsx-vneg.c | 321 ++++ .../loongarch/vector/lsx/lsx-vnor.c | 109 ++ .../loongarch/vector/lsx/lsx-vnori.c | 91 + .../gcc.target/loongarch/vector/lsx/lsx-vor.c | 169 ++ .../loongarch/vector/lsx/lsx-vori.c | 123 ++ .../loongarch/vector/lsx/lsx-vorn.c | 109 ++ .../loongarch/vector/lsx/lsx-vpackev.c | 452 +++++ .../loongarch/vector/lsx/lsx-vpackod.c | 461 ++++++ .../loongarch/vector/lsx/lsx-vpcnt.c | 350 ++++ .../loongarch/vector/lsx/lsx-vpickev.c | 362 ++++ .../loongarch/vector/lsx/lsx-vpickod.c | 336 ++++ .../loongarch/vector/lsx/lsx-vpickve2gr.c | 488 ++++++ .../loongarch/vector/lsx/lsx-vpremi.c | 20 + .../loongarch/vector/lsx/lsx-vreplgr2vr.c | 212 +++ .../loongarch/vector/lsx/lsx-vreplve.c | 300 ++++ .../loongarch/vector/lsx/lsx-vreplvei.c | 293 ++++ .../loongarch/vector/lsx/lsx-vrotr.c | 381 +++++ .../loongarch/vector/lsx/lsx-vrotri.c | 294 ++++ .../loongarch/vector/lsx/lsx-vsadd-1.c | 335 ++++ .../loongarch/vector/lsx/lsx-vsadd-2.c | 345 ++++ .../loongarch/vector/lsx/lsx-vsat-1.c | 231 +++ .../loongarch/vector/lsx/lsx-vsat-2.c | 272 +++ .../loongarch/vector/lsx/lsx-vseq.c | 470 ++++++ .../loongarch/vector/lsx/lsx-vseqi.c | 328 ++++ .../loongarch/vector/lsx/lsx-vshuf.c | 394 +++++ .../loongarch/vector/lsx/lsx-vshuf4i.c | 348 ++++ .../loongarch/vector/lsx/lsx-vsigncov.c | 425 +++++ .../loongarch/vector/lsx/lsx-vsle-1.c | 290 ++++ .../loongarch/vector/lsx/lsx-vsle-2.c | 444 +++++ .../loongarch/vector/lsx/lsx-vslei-1.c | 258 +++ .../loongarch/vector/lsx/lsx-vslei-2.c | 293 ++++ .../loongarch/vector/lsx/lsx-vsll.c | 254 +++ .../loongarch/vector/lsx/lsx-vslli.c | 293 ++++ .../loongarch/vector/lsx/lsx-vsllwil-1.c | 244 +++ .../loongarch/vector/lsx/lsx-vsllwil-2.c | 189 +++ .../loongarch/vector/lsx/lsx-vslt-1.c | 434 +++++ .../loongarch/vector/lsx/lsx-vslt-2.c | 236 +++ .../loongarch/vector/lsx/lsx-vslti-1.c | 328 ++++ .../loongarch/vector/lsx/lsx-vslti-2.c | 293 ++++ .../loongarch/vector/lsx/lsx-vsra.c | 344 ++++ .../loongarch/vector/lsx/lsx-vsrai.c | 258 +++ .../loongarch/vector/lsx/lsx-vsran.c | 290 ++++ .../loongarch/vector/lsx/lsx-vsrani.c | 246 +++ .../loongarch/vector/lsx/lsx-vsrar.c | 354 ++++ .../loongarch/vector/lsx/lsx-vsrari.c | 265 +++ .../loongarch/vector/lsx/lsx-vsrarn.c | 236 +++ .../loongarch/vector/lsx/lsx-vsrarni.c | 398 +++++ .../loongarch/vector/lsx/lsx-vsrl.c | 389 +++++ .../loongarch/vector/lsx/lsx-vsrli.c | 328 ++++ .../loongarch/vector/lsx/lsx-vsrln.c | 335 ++++ .../loongarch/vector/lsx/lsx-vsrlni.c | 281 ++++ .../loongarch/vector/lsx/lsx-vsrlr.c | 434 +++++ .../loongarch/vector/lsx/lsx-vsrlri.c | 300 ++++ .../loongarch/vector/lsx/lsx-vsrlrn.c | 164 ++ .../loongarch/vector/lsx/lsx-vsrlrni.c | 686 ++++++++ .../loongarch/vector/lsx/lsx-vssran.c | 390 +++++ .../loongarch/vector/lsx/lsx-vssrani.c | 679 ++++++++ .../loongarch/vector/lsx/lsx-vssrarn.c | 669 ++++++++ .../loongarch/vector/lsx/lsx-vssrarni.c | 848 ++++++++++ .../loongarch/vector/lsx/lsx-vssrln.c | 543 ++++++ .../loongarch/vector/lsx/lsx-vssrlni.c | 668 ++++++++ .../loongarch/vector/lsx/lsx-vssrlrn.c | 470 ++++++ .../loongarch/vector/lsx/lsx-vssrlrni.c | 597 +++++++ .../loongarch/vector/lsx/lsx-vssub-1.c | 398 +++++ .../loongarch/vector/lsx/lsx-vssub-2.c | 408 +++++ .../gcc.target/loongarch/vector/lsx/lsx-vst.c | 70 + .../loongarch/vector/lsx/lsx-vsub.c | 381 +++++ .../loongarch/vector/lsx/lsx-vsubi.c | 329 ++++ .../loongarch/vector/lsx/lsx-vsubwev-1.c | 326 ++++ .../loongarch/vector/lsx/lsx-vsubwev-2.c | 417 +++++ .../loongarch/vector/lsx/lsx-vsubwod-1.c | 326 ++++ .../loongarch/vector/lsx/lsx-vsubwod-2.c | 308 ++++ .../loongarch/vector/lsx/lsx-vxor.c | 79 + .../loongarch/vector/lsx/lsx-vxori.c | 67 + .../loongarch/vector/simd_correctness_check.h | 54 + 197 files changed, 62937 insertions(+) create mode 100644 gcc/testsuite/gcc.target/loongarch/strict-align.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/loongarch-vector.exp create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-builtin.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vabsd-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vabsd-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vadd.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vadda.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vaddi.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vaddwev-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vaddwev-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vaddwev-3.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vaddwod-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vaddwod-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vaddwod-3.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vand.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vandi.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vandn.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vavg-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vavg-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vavgr-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vavgr-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vbitclr.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vbitclri.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vbitrev.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vbitrevi.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vbitsel.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vbitseli.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vbitset.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vbitseti.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vbsll.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vbsrl.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vclo.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vclz.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vdiv-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vdiv-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vexth-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vexth-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vextl-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vextl-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vextrins.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfadd_d.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfadd_s.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfclass_d.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfclass_s.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfcmp_caf.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfcmp_ceq.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfcmp_cle.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfcmp_clt.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfcmp_cne.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfcmp_cor.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfcmp_cun.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfcmp_saf.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfcmp_seq.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfcmp_sle.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfcmp_slt.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfcmp_sne.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfcmp_sor.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfcmp_sun.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfcvt-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfcvt-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vffint-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vffint-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vffint-3.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vflogb_d.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vflogb_s.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfmadd_d.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfmadd_s.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfmax_d.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfmax_s.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfmaxa_d.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfmaxa_s.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfnmadd_d.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfnmadd_s.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfrint_d.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfrint_s.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfrstp.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfrstpi.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfsqrt_d.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfsqrt_s.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vftint-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vftint-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vftint-3.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vftint-4.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vhaddw-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vhaddw-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vhsubw-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vhsubw-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vilvh.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vilvl.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vinsgr2vr.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vld.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vldi.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmadd.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmaddwev-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmaddwev-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmaddwev-3.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmaddwod-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmaddwod-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmaddwod-3.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmax-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmax-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmaxi-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmaxi-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmin-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmin-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmini-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmini-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmod-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmod-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmskgez.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmskltz.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmsknz.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmsub.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmuh-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmuh-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmul.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmulwev-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmulwev-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmulwev-3.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmulwod-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmulwod-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmulwod-3.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vneg.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vnor.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vnori.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vor.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vori.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vorn.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vpackev.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vpackod.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vpcnt.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vpickev.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vpickod.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vpickve2gr.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vpremi.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vreplgr2vr.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vreplve.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vreplvei.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vrotr.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vrotri.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsadd-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsadd-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsat-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsat-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vseq.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vseqi.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vshuf.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vshuf4i.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsigncov.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsle-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsle-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vslei-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vslei-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsll.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vslli.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsllwil-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsllwil-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vslt-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vslt-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vslti-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vslti-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsra.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsrai.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsran.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsrani.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsrar.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsrari.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsrarn.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsrarni.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsrl.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsrli.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsrln.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsrlni.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsrlr.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsrlri.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsrlrn.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsrlrni.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vssran.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vssrani.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vssrarn.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vssrarni.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vssrln.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vssrlni.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vssrlrn.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vssrlrni.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vssub-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vssub-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vst.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsub.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsubi.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsubwev-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsubwev-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsubwod-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsubwod-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vxor.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vxori.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/simd_correctness_check.h