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From: Xiaolong Chen <chenxiaolong@loongson.cn>
To: gcc-patches@gcc.gnu.org
Subject: [PATCH v1 0/4] Add Loongson SX/ASX instruction support to LoongArch
Date: Wed, 6 Sep 2023 18:43:03 +0800
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| Series |
Add Loongson SX/ASX instruction support to LoongArch
|
|
Message
chenxiaolong
Sept. 6, 2023, 10:43 a.m. UTC
In order to better test the function of the vector instruction, the 128 and 256
bit test cases are further split according to the function of the instruction.
Xiaolong Chen (4):
LoongArch: Add tests of -mstrict-align option.
LoongArch: Add testsuite framework for Loongson SX/ASX.
LoongArch: Add tests for Loongson SX builtin functions.
LoongArch: Add tests for Loongson SX floating-point conversion
instructions.
.../gcc.target/loongarch/strict-align.c | 13 +
.../loongarch/vector/loongarch-vector.exp | 42 +
.../loongarch/vector/lsx/lsx-builtin.c | 1461 +++++++++++++++++
.../loongarch/vector/lsx/lsx-vfcvt-1.c | 397 +++++
.../loongarch/vector/lsx/lsx-vfcvt-2.c | 277 ++++
.../loongarch/vector/lsx/lsx-vffint-1.c | 160 ++
.../loongarch/vector/lsx/lsx-vffint-2.c | 263 +++
.../loongarch/vector/lsx/lsx-vffint-3.c | 101 ++
.../loongarch/vector/lsx/lsx-vfrint_d.c | 229 +++
.../loongarch/vector/lsx/lsx-vfrint_s.c | 349 ++++
.../loongarch/vector/lsx/lsx-vftint-1.c | 348 ++++
.../loongarch/vector/lsx/lsx-vftint-2.c | 694 ++++++++
.../loongarch/vector/lsx/lsx-vftint-3.c | 1027 ++++++++++++
.../loongarch/vector/lsx/lsx-vftint-4.c | 344 ++++
.../loongarch/vector/simd_correctness_check.h | 39 +
15 files changed, 5744 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/loongarch/strict-align.c
create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/loongarch-vector.exp
create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-builtin.c
create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfcvt-1.c
create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfcvt-2.c
create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vffint-1.c
create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vffint-2.c
create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vffint-3.c
create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfrint_d.c
create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfrint_s.c
create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vftint-1.c
create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vftint-2.c
create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vftint-3.c
create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vftint-4.c
create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/simd_correctness_check.h