mbox series

[v2,0/8] RISCV: Implement ISA Manual Table A.6 Mappings

Message ID 20230405210118.1969283-1-patrick@rivosinc.com
Headers
Series RISCV: Implement ISA Manual Table A.6 Mappings |

Message

Patrick O'Neill April 5, 2023, 9:01 p.m. UTC 
  This patchset aims to bring the RISCV atomics implementation in line
with the recommended mapping present in table A.6 of the ISA manual.
  https://github.com/riscv/riscv-isa-manual/blob/c7cf84547b3aefacab5463add1734c1602b67a49/src/memory.tex#L1083-L1157

The current mapping in GCC is not internally consistent. Andrea Parri
pointed this out here along with a litmus test:
  https://inbox.sourceware.org/gcc-patches/Y1GbJuhcBFpPGJQ0@andrea/

As a result, we have an opportunity to jump straight to the A.6
implementation (meaning we will be compatible with LLVM's mappings which
are A.6). Ideally we move to the A.6 mappings before more binaries are
built/distributed and it becomes more painful to switch.

Patch 1 simplifies the memmodel to ignore MEMMODEL_SYNC_* cases (legacy
cases that aren't handled differently for RISC-V).
Patches 2-4 make the mappings strictly stronger.
Patches 5-8 weaken the mappings to be in line with table A.6 of the ISA
manual.

Christoph Muellner also submitted a similar patchset here:
  https://gcc.gnu.org/pipermail/gcc-patches/2022-May/595712.html
I used my previous patchset as a starting point since it was easier for 
me.

LLVM mapping notes:
* LLVM emits corresponding fences for atomic_signal_fence instructions.
  This seems to be an oversight since AFAIK atomic_signal_fence acts as
  a compiler directive. GCC does not emit any fences for
  atomic_signal_fence instructions.

Remaining work:
* After this patchset, GCC still emits a full fence rw,rw after a
  SEQ_CST load (fence r,rw is recommended by table A.6).
  This can be relaxed in a future patch as it is strictly stronger than
  A.6's recommendation - I wanted to get this series out to be
  considered for GCC 13.

Patchset v1:
  https://gcc.gnu.org/pipermail/gcc-patches/2022-April/592950.html

Changes for v2:
* Use memmodel_base rather than a custom simplify_memmodel function
  (Inspired by Christoph Muellner's patch 1/9)
* Move instruction styling change from [v1 5/7] to [v2 3/8] to reduce
  [v2 6/8]'s complexity
* Eliminated %K flag for atomic store introduced in v1 in favor of
  if/else
* Rebase/test

* PR target/89835: The RISC-V target uses amoswap.w for relaxed stores

Patrick O'Neill (8):
  RISCV: Eliminate SYNC memory models
  RISCV: Enforce Libatomic LR/SC SEQ_CST
  RISCV: Enforce atomic compare_exchange SEQ_CST
  RISCV: Add AMO release bits
  RISCV: Eliminate AMO op fences
  RISCV: Weaken compare_exchange LR/SC pairs
  RISCV: Weaken atomic stores
  RISCV: Weaken mem_thread_fence

 gcc/config/riscv/riscv-protos.h               |  5 ++
 gcc/config/riscv/riscv.cc                     | 70 ++++++++++++++-----
 gcc/config/riscv/sync.md                      | 62 +++++++++++-----
 .../gcc.target/riscv/amo-thread-fence-1.c     |  6 ++
 .../gcc.target/riscv/amo-thread-fence-2.c     |  6 ++
 .../gcc.target/riscv/amo-thread-fence-3.c     |  6 ++
 .../gcc.target/riscv/amo-thread-fence-4.c     |  6 ++
 .../gcc.target/riscv/amo-thread-fence-5.c     |  6 ++
 .../riscv/compare-exchange-atomics-model-1.c  | 12 ++++
 .../riscv/compare-exchange-atomics-model-2.c  | 12 ++++
 .../riscv/compare-exchange-atomics-model-3.c  | 12 ++++
 .../riscv/compare-exchange-atomics-model-4.c  | 12 ++++
 .../riscv/compare-exchange-atomics-model-5.c  | 12 ++++
 gcc/testsuite/gcc.target/riscv/pr89835.c      |  9 +++
 libgcc/config/riscv/atomic.c                  |  4 +-
 15 files changed, 206 insertions(+), 34 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-thread-fence-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-thread-fence-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-thread-fence-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-thread-fence-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-thread-fence-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/compare-exchange-atomics-model-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/compare-exchange-atomics-model-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/compare-exchange-atomics-model-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/compare-exchange-atomics-model-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/compare-exchange-atomics-model-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/pr89835.c