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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id p17-20020a170906229100b008e68d2c11d8sm6853872eja.218.2023.03.02.00.35.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Mar 2023 00:35:37 -0800 (PST) From: Christoph Muellner To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Palmer Dabbelt , Andrew Waterman , Philipp Tomsich , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu , Andrew Pinski , Hans-Peter Nilsson Cc: =?utf-8?q?Christoph_M=C3=BCllner?= Subject: [PATCH v4 0/9] RISC-V: Add XThead* extension support Date: Thu, 2 Mar 2023 09:35:25 +0100 Message-Id: <20230302083534.4076244-1-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 X-Spam-Status: No, score=-6.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, JMQ_SPF_NEUTRAL, KAM_MANYTO, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759244398963057102?= X-GMAIL-MSGID: =?utf-8?q?1759244398963057102?= From: Christoph Müllner This series introduces support for the T-Head specific RISC-V ISA extensions which are available e.g. on the T-Head XuanTie C906. The ISA spec can be found here: https://github.com/T-head-Semi/thead-extension-spec This series adds support for the following XThead* extensions: * XTheadBa * XTheadBb * XTheadBs * XTheadCmo * XTheadCondMov * XTheadFmv * XTheadInt * XTheadMac * XTheadMemPair * XTheadSync All extensions are properly integrated and the included tests demonstrate the improvements of the generated code. The series also introduces support for "-mcpu=thead-c906", which also enables all available XThead* ISA extensions of the T-Head C906. All patches have been tested and don't introduce regressions for RV32 or RV64. The patches have also been tested with SPEC CPU2017 on QEMU and real HW (D1 board). Support patches for these extensions for Binutils, QEMU, and LLVM have already been merged in the corresponding upstream projects. Patches 1-8 from this series (everything except the last one) got an ACK by Kito. However, since there were a few comments after the ACK, I decided to send out a v4, so that reviewers can verify that their comments have been addressed properly. Note, that there was a concern raised by Andrew Pinski (on CC), which might not be resolved with this series (I could not reproduce the issue, but I might have misunderstood something). Changes in v4: - Drop XTheadMemIdx and XTheadFMemIdx (will be a follow-up series) - Replace 'immediate_operand' by 'const_int_operand' in many patterns - Small cleanups in XTheadBb - Factor out C code into thead.cc (XTheadMemPair) to minimize changes in riscv.cc Changes in v3: - Bugfix in XTheadBa - Rewrite of XTheadMemPair - Inclusion of XTheadMemIdx and XTheadFMemIdx Christoph Müllner (9): riscv: Add basic XThead* vendor extension support riscv: riscv-cores.def: Add T-Head XuanTie C906 riscv: thead: Add support for the XTheadBa ISA extension riscv: thead: Add support for the XTheadBs ISA extension riscv: thead: Add support for the XTheadBb ISA extension riscv: thead: Add support for the XTheadCondMov ISA extensions riscv: thead: Add support for the XTheadMac ISA extension riscv: thead: Add support for the XTheadFmv ISA extension riscv: thead: Add support for the XTheadMemPair ISA extension gcc/common/config/riscv/riscv-common.cc | 26 ++ gcc/config.gcc | 1 + gcc/config/riscv/bitmanip.md | 52 ++- gcc/config/riscv/constraints.md | 8 + gcc/config/riscv/iterators.md | 4 + gcc/config/riscv/peephole.md | 56 +++ gcc/config/riscv/riscv-cores.def | 4 + gcc/config/riscv/riscv-opts.h | 26 ++ gcc/config/riscv/riscv-protos.h | 16 +- gcc/config/riscv/riscv.cc | 226 +++++++-- gcc/config/riscv/riscv.md | 67 ++- gcc/config/riscv/riscv.opt | 3 + gcc/config/riscv/t-riscv | 4 + gcc/config/riscv/thead.cc | 427 ++++++++++++++++++ gcc/config/riscv/thead.md | 346 ++++++++++++++ .../gcc.target/riscv/mcpu-thead-c906.c | 28 ++ .../gcc.target/riscv/xtheadba-addsl.c | 55 +++ gcc/testsuite/gcc.target/riscv/xtheadba.c | 14 + gcc/testsuite/gcc.target/riscv/xtheadbb-ext.c | 20 + .../gcc.target/riscv/xtheadbb-extu-2.c | 22 + .../gcc.target/riscv/xtheadbb-extu.c | 22 + gcc/testsuite/gcc.target/riscv/xtheadbb-ff1.c | 18 + gcc/testsuite/gcc.target/riscv/xtheadbb-rev.c | 45 ++ .../gcc.target/riscv/xtheadbb-srri.c | 25 + gcc/testsuite/gcc.target/riscv/xtheadbb.c | 14 + gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c | 13 + gcc/testsuite/gcc.target/riscv/xtheadbs.c | 14 + gcc/testsuite/gcc.target/riscv/xtheadcmo.c | 14 + .../riscv/xtheadcondmov-mveqz-imm-eqz.c | 38 ++ .../riscv/xtheadcondmov-mveqz-imm-not.c | 38 ++ .../riscv/xtheadcondmov-mveqz-reg-eqz.c | 38 ++ .../riscv/xtheadcondmov-mveqz-reg-not.c | 38 ++ .../riscv/xtheadcondmov-mvnez-imm-cond.c | 38 ++ .../riscv/xtheadcondmov-mvnez-imm-nez.c | 38 ++ .../riscv/xtheadcondmov-mvnez-reg-cond.c | 38 ++ .../riscv/xtheadcondmov-mvnez-reg-nez.c | 38 ++ .../gcc.target/riscv/xtheadcondmov.c | 14 + .../gcc.target/riscv/xtheadfmemidx.c | 14 + .../gcc.target/riscv/xtheadfmv-fmv.c | 24 + gcc/testsuite/gcc.target/riscv/xtheadfmv.c | 14 + gcc/testsuite/gcc.target/riscv/xtheadint.c | 14 + .../gcc.target/riscv/xtheadmac-mula-muls.c | 43 ++ gcc/testsuite/gcc.target/riscv/xtheadmac.c | 14 + gcc/testsuite/gcc.target/riscv/xtheadmemidx.c | 14 + .../gcc.target/riscv/xtheadmempair-1.c | 98 ++++ .../gcc.target/riscv/xtheadmempair-2.c | 84 ++++ .../gcc.target/riscv/xtheadmempair-3.c | 29 ++ .../gcc.target/riscv/xtheadmempair.c | 13 + gcc/testsuite/gcc.target/riscv/xtheadsync.c | 14 + 49 files changed, 2196 insertions(+), 67 deletions(-) create mode 100644 gcc/config/riscv/thead.cc create mode 100644 gcc/config/riscv/thead.md create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadba-addsl.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadba.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-ext.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-extu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-extu.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-ff1.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-rev.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-srri.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbs.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcmo.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-imm-eqz.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-imm-not.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-reg-eqz.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-reg-not.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-imm-cond.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-imm-nez.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-reg-cond.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-reg-nez.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmv.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadint.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmac-mula-muls.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmac.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadsync.c