[00/35] arm: rework MVE testsuite and rework backend where necessary (1st chunk)

Message ID	20221117163809.1009526-1-andrea.corallo@arm.com
Headers	Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 05D563AA9414 Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 40.67.248.234 as permitted sender) receiver=protection.outlook.com; client-ip=40.67.248.234; helo=nebula.arm.com; pr=C To: <gcc-patches@gcc.gnu.org> CC: <kyrylo.tkachov@arm.com>, <Richard.Earnshaw@arm.com>, Andrea Corallo <andrea.corallo@arm.com> Subject: [PATCH 00/35] arm: rework MVE testsuite and rework backend where necessary (1st chunk) Date: Thu, 17 Nov 2022 17:37:34 +0100 Message-ID: <20221117163809.1009526-1-andrea.corallo@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain NoDisclaimer: true Precedence: list From: Andrea Corallo via Gcc-patches <gcc-patches@gcc.gnu.org> Reply-To: Andrea Corallo <andrea.corallo@arm.com> Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" <gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org> X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?=
Series	arm: rework MVE testsuite and rework backend where necessary (1st chunk) \| [00/35] arm: rework MVE testsuite and rework backend where necessary (1st chunk) [01/35] arm: improve vcreateq* tests [02/35] arm: fix 'vmsr' spacing and register capitalization [03/35] arm: improve tests and fix vddupq* [04/35] arm: improve tests and fix vdwdupq* [05/35] arm: improve vidupq* tests [06/35] arm: improve tests and fix vdupq* [07/35] arm: improve tests and fix vcmp* [08/35] arm: improve tests for vmin* [09/35] arm: improve tests for vmax* [10/35] arm: improve tests for vabavq* [11/35] arm: improve tests for vabdq* [12/35] arm: improve tests and fix vabsq* [13/35] arm: further fix overloading of MVE vaddq[_m]_n intrinsic [14/35] arm: propagate fixed overloading of MVE intrinsic scalar parameters [15/35] arm: Explicitly specify other float types for _Generic overloading [PR107515] [16/35] arm: Add integer vector overloading of vsubq_x instrinsic [17/35] arm: improve tests and fix vadd* [18/35] arm: improve tests for vmulq* [19/35] arm: improve tests and fix vsubq* [20/35] arm: improve tests for vfmasq_m* [21/35] arm: improve tests for vhaddq_m* [22/35] arm: improve tests for vhsubq_m* [23/35] arm: improve tests for viwdupq* [24/35] arm: improve tests for vmladavaq* [25/35] arm: improve tests and fix vmlaldavaxq* [26/35] arm: improve tests for vmlasq* [27/35] arm: improve tests for vqaddq_m* [28/35] arm: improve tests for vqdmlahq_m* [29/35] arm: improve tests for vqdmul* [30/35] arm: improve tests for vqrdmlahq* [31/35] arm: improve tests for vqrdmlashq_m* [32/35] arm: improve tests for vqsubq* [33/35] arm: improve tests and fix vrmlaldavhaq* [34/35] arm: improve tests for vrshlq* [35/35] arm: improve tests for vsetq_lane*

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20221117163809.1009526-1-andrea.corallo@arm.com

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Subject: [PATCH 00/35] arm: rework MVE testsuite and rework backend where
 necessary (1st chunk)
Date: Thu, 17 Nov 2022 17:37:34 +0100
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Series

arm: rework MVE testsuite and rework backend where necessary (1st chunk) |

Message

Andrea Corallo Nov. 17, 2022, 4:37 p.m. UTC

  Hi all,

this is the first patch series about improving the current MVE
implementation and testsuite for:

- Complete intrinsic implementation and coverage (the list of intrinsics is
  specified by [1])
- Verifying all instructions supposedly emitted by each intrinsic
- Verifying register usage
- Fixing the current scan assemblers to really match the wanted mnemonics
- Verifying no external calls are emitted

This series fixes the backend where necessary.

Best Regards

  Andrea

Andrea Corallo (31):
  arm: improve vcreateq* tests
  arm: fix 'vmsr' spacing and register capitalization
  arm: improve tests and fix vddupq*
  arm: improve tests and fix vdwdupq*
  arm: improve vidupq* tests
  arm: improve tests and fix vdupq*
  arm: improve tests and fix vcmp*
  arm: improve tests for vmin*
  arm: improve tests for vmax*
  arm: improve tests for vabavq*
  arm: improve tests for vabdq*
  arm: improve tests and fix vabsq*
  arm: improve tests and fix vadd*
  arm: improve tests for vmulq*
  arm: improve tests and fix vsubq*
  arm: improve tests for vfmasq_m*
  arm: improve tests for vhaddq_m*
  arm: improve tests for vhsubq_m*
  arm: improve tests for viwdupq*
  arm: improve tests for vmladavaq*
  arm: improve tests and fix vmlaldavaxq*
  arm: improve tests for vmlasq*
  arm: improve tests for vqaddq_m*
  arm: improve tests for vqdmlahq_m*
  arm: improve tests for vqdmul*
  arm: improve tests for vqrdmlahq*
  arm: improve tests for vqrdmlashq_m*
  arm: improve tests for vqsubq*
  arm: improve tests and fix vrmlaldavhaq*
  arm: improve tests for vrshlq*
  arm: improve tests for vsetq_lane*

Stam Markianos-Wright (4):
  arm: further fix overloading of MVE vaddq[_m]_n intrinsic
  arm: propagate fixed overloading of MVE intrinsic scalar parameters
  arm: Explicitly specify other float types for _Generic overloading
    [PR107515]
  arm: Add integer vector overloading of vsubq_x instrinsic

 gcc/config/arm/arm_mve.h                      | 1232 +++++++++--------
 gcc/config/arm/mve.md                         |   48 +-
 gcc/config/arm/vfp.md                         |    8 +-
 .../arm/mve/intrinsics/vabavq_p_s16.c         |   40 +-
 .../arm/mve/intrinsics/vabavq_p_s32.c         |   40 +-
 .../arm/mve/intrinsics/vabavq_p_s8.c          |   40 +-
 .../arm/mve/intrinsics/vabavq_p_u16.c         |   40 +-
 .../arm/mve/intrinsics/vabavq_p_u32.c         |   40 +-
 .../arm/mve/intrinsics/vabavq_p_u8.c          |   40 +-
 .../arm/mve/intrinsics/vabavq_s16.c           |   28 +-
 .../arm/mve/intrinsics/vabavq_s32.c           |   28 +-
 .../gcc.target/arm/mve/intrinsics/vabavq_s8.c |   28 +-
 .../arm/mve/intrinsics/vabavq_u16.c           |   28 +-
 .../arm/mve/intrinsics/vabavq_u32.c           |   28 +-
 .../gcc.target/arm/mve/intrinsics/vabavq_u8.c |   28 +-
 .../gcc.target/arm/mve/intrinsics/vabdq_f16.c |   16 +-
 .../gcc.target/arm/mve/intrinsics/vabdq_f32.c |   16 +-
 .../arm/mve/intrinsics/vabdq_m_f16.c          |   26 +-
 .../arm/mve/intrinsics/vabdq_m_f32.c          |   26 +-
 .../arm/mve/intrinsics/vabdq_m_s16.c          |   26 +-
 .../arm/mve/intrinsics/vabdq_m_s32.c          |   26 +-
 .../arm/mve/intrinsics/vabdq_m_s8.c           |   26 +-
 .../arm/mve/intrinsics/vabdq_m_u16.c          |   26 +-
 .../arm/mve/intrinsics/vabdq_m_u32.c          |   26 +-
 .../arm/mve/intrinsics/vabdq_m_u8.c           |   26 +-
 .../gcc.target/arm/mve/intrinsics/vabdq_s16.c |   16 +-
 .../gcc.target/arm/mve/intrinsics/vabdq_s32.c |   16 +-
 .../gcc.target/arm/mve/intrinsics/vabdq_s8.c  |   16 +-
 .../gcc.target/arm/mve/intrinsics/vabdq_u16.c |   16 +-
 .../gcc.target/arm/mve/intrinsics/vabdq_u32.c |   16 +-
 .../gcc.target/arm/mve/intrinsics/vabdq_u8.c  |   16 +-
 .../arm/mve/intrinsics/vabdq_x_f16.c          |   25 +-
 .../arm/mve/intrinsics/vabdq_x_f32.c          |   25 +-
 .../arm/mve/intrinsics/vabdq_x_s16.c          |   26 +-
 .../arm/mve/intrinsics/vabdq_x_s32.c          |   25 +-
 .../arm/mve/intrinsics/vabdq_x_s8.c           |   25 +-
 .../arm/mve/intrinsics/vabdq_x_u16.c          |   25 +-
 .../arm/mve/intrinsics/vabdq_x_u32.c          |   25 +-
 .../arm/mve/intrinsics/vabdq_x_u8.c           |   25 +-
 .../gcc.target/arm/mve/intrinsics/vabsq_f16.c |   22 +-
 .../gcc.target/arm/mve/intrinsics/vabsq_f32.c |   22 +-
 .../arm/mve/intrinsics/vabsq_m_f16.c          |   25 +-
 .../arm/mve/intrinsics/vabsq_m_f32.c          |   25 +-
 .../arm/mve/intrinsics/vabsq_m_s16.c          |   25 +-
 .../arm/mve/intrinsics/vabsq_m_s32.c          |   25 +-
 .../arm/mve/intrinsics/vabsq_m_s8.c           |   25 +-
 .../gcc.target/arm/mve/intrinsics/vabsq_s16.c |   20 +-
 .../gcc.target/arm/mve/intrinsics/vabsq_s32.c |   20 +-
 .../gcc.target/arm/mve/intrinsics/vabsq_s8.c  |   16 +-
 .../arm/mve/intrinsics/vabsq_x_f16.c          |   25 +-
 .../arm/mve/intrinsics/vabsq_x_f32.c          |   25 +-
 .../arm/mve/intrinsics/vabsq_x_s16.c          |   25 +-
 .../arm/mve/intrinsics/vabsq_x_s32.c          |   25 +-
 .../arm/mve/intrinsics/vabsq_x_s8.c           |   25 +-
 .../arm/mve/intrinsics/vaddlvaq_p_s32.c       |   24 +-
 .../arm/mve/intrinsics/vaddlvaq_p_u32.c       |   40 +-
 .../arm/mve/intrinsics/vaddlvaq_s32.c         |   16 +-
 .../arm/mve/intrinsics/vaddlvaq_u32.c         |   28 +-
 .../arm/mve/intrinsics/vaddlvq_p_s32.c        |   24 +-
 .../arm/mve/intrinsics/vaddlvq_p_u32.c        |   24 +-
 .../arm/mve/intrinsics/vaddlvq_s32.c          |   22 +-
 .../arm/mve/intrinsics/vaddlvq_u32.c          |   20 +-
 .../gcc.target/arm/mve/intrinsics/vaddq_f16.c |   16 +-
 .../gcc.target/arm/mve/intrinsics/vaddq_f32.c |   16 +-
 .../arm/mve/intrinsics/vaddq_m_f16.c          |   26 +-
 .../arm/mve/intrinsics/vaddq_m_f32.c          |   26 +-
 .../arm/mve/intrinsics/vaddq_m_n_f16.c        |   42 +-
 .../arm/mve/intrinsics/vaddq_m_n_f32.c        |   42 +-
 .../arm/mve/intrinsics/vaddq_m_n_s16.c        |   26 +-
 .../arm/mve/intrinsics/vaddq_m_n_s32.c        |   26 +-
 .../arm/mve/intrinsics/vaddq_m_n_s8.c         |   26 +-
 .../arm/mve/intrinsics/vaddq_m_n_u16.c        |   42 +-
 .../arm/mve/intrinsics/vaddq_m_n_u32.c        |   42 +-
 .../arm/mve/intrinsics/vaddq_m_n_u8.c         |   42 +-
 .../arm/mve/intrinsics/vaddq_m_s16.c          |   26 +-
 .../arm/mve/intrinsics/vaddq_m_s32.c          |   26 +-
 .../arm/mve/intrinsics/vaddq_m_s8.c           |   26 +-
 .../arm/mve/intrinsics/vaddq_m_u16.c          |   26 +-
 .../arm/mve/intrinsics/vaddq_m_u32.c          |   26 +-
 .../arm/mve/intrinsics/vaddq_m_u8.c           |   26 +-
 .../arm/mve/intrinsics/vaddq_n_f16.c          |   28 +-
 .../arm/mve/intrinsics/vaddq_n_f32.c          |   28 +-
 .../arm/mve/intrinsics/vaddq_n_s16.c          |   16 +-
 .../arm/mve/intrinsics/vaddq_n_s32.c          |   16 +-
 .../arm/mve/intrinsics/vaddq_n_s8.c           |   16 +-
 .../arm/mve/intrinsics/vaddq_n_u16.c          |   28 +-
 .../arm/mve/intrinsics/vaddq_n_u32.c          |   28 +-
 .../arm/mve/intrinsics/vaddq_n_u8.c           |   28 +-
 .../gcc.target/arm/mve/intrinsics/vaddq_s16.c |   16 +-
 .../gcc.target/arm/mve/intrinsics/vaddq_s32.c |   16 +-
 .../gcc.target/arm/mve/intrinsics/vaddq_s8.c  |   16 +-
 .../gcc.target/arm/mve/intrinsics/vaddq_u16.c |   16 +-
 .../gcc.target/arm/mve/intrinsics/vaddq_u32.c |   16 +-
 .../gcc.target/arm/mve/intrinsics/vaddq_u8.c  |   16 +-
 .../arm/mve/intrinsics/vaddq_x_f16.c          |   26 +-
 .../arm/mve/intrinsics/vaddq_x_f32.c          |   26 +-
 .../arm/mve/intrinsics/vaddq_x_n_f16.c        |   42 +-
 .../arm/mve/intrinsics/vaddq_x_n_f32.c        |   42 +-
 .../arm/mve/intrinsics/vaddq_x_n_s16.c        |   26 +-
 .../arm/mve/intrinsics/vaddq_x_n_s32.c        |   26 +-
 .../arm/mve/intrinsics/vaddq_x_n_s8.c         |   26 +-
 .../arm/mve/intrinsics/vaddq_x_n_u16.c        |   42 +-
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 .../arm/mve/intrinsics/vmulq_m_n_u8.c         |   42 +-
 .../arm/mve/intrinsics/vmulq_m_s16.c          |   26 +-
 .../arm/mve/intrinsics/vmulq_m_s32.c          |   26 +-
 .../arm/mve/intrinsics/vmulq_m_s8.c           |   26 +-
 .../arm/mve/intrinsics/vmulq_m_u16.c          |   26 +-
 .../arm/mve/intrinsics/vmulq_m_u32.c          |   26 +-
 .../arm/mve/intrinsics/vmulq_m_u8.c           |   26 +-
 .../arm/mve/intrinsics/vmulq_n_f16.c          |   28 +-
 .../arm/mve/intrinsics/vmulq_n_f32.c          |   28 +-
 .../arm/mve/intrinsics/vmulq_n_s16.c          |   16 +-
 .../arm/mve/intrinsics/vmulq_n_s32.c          |   16 +-
 .../arm/mve/intrinsics/vmulq_n_s8.c           |   16 +-
 .../arm/mve/intrinsics/vmulq_n_u16.c          |   28 +-
 .../arm/mve/intrinsics/vmulq_n_u32.c          |   28 +-
 .../arm/mve/intrinsics/vmulq_n_u8.c           |   28 +-
 .../gcc.target/arm/mve/intrinsics/vmulq_s16.c |   16 +-
 .../gcc.target/arm/mve/intrinsics/vmulq_s32.c |   16 +-
 .../gcc.target/arm/mve/intrinsics/vmulq_s8.c  |   16 +-
 .../gcc.target/arm/mve/intrinsics/vmulq_u16.c |   16 +-
 .../gcc.target/arm/mve/intrinsics/vmulq_u32.c |   16 +-
 .../gcc.target/arm/mve/intrinsics/vmulq_u8.c  |   16 +-
 .../arm/mve/intrinsics/vmulq_x_f16.c          |   26 +-
 .../arm/mve/intrinsics/vmulq_x_f32.c          |   26 +-
 .../arm/mve/intrinsics/vmulq_x_n_f16.c        |   42 +-
 .../arm/mve/intrinsics/vmulq_x_n_f32.c        |   42 +-
 .../arm/mve/intrinsics/vmulq_x_n_s16.c        |   26 +-
 .../arm/mve/intrinsics/vmulq_x_n_s32.c        |   26 +-
 .../arm/mve/intrinsics/vmulq_x_n_s8.c         |   26 +-
 .../arm/mve/intrinsics/vmulq_x_n_u16.c        |   42 +-
 .../arm/mve/intrinsics/vmulq_x_n_u32.c        |   42 +-
 .../arm/mve/intrinsics/vmulq_x_n_u8.c         |   42 +-
 .../arm/mve/intrinsics/vmulq_x_s16.c          |   26 +-
 .../arm/mve/intrinsics/vmulq_x_s32.c          |   26 +-
 .../arm/mve/intrinsics/vmulq_x_s8.c           |   26 +-
 .../arm/mve/intrinsics/vmulq_x_u16.c          |   26 +-
 .../arm/mve/intrinsics/vmulq_x_u32.c          |   26 +-
 .../arm/mve/intrinsics/vmulq_x_u8.c           |   26 +-
 .../arm/mve/intrinsics/vqaddq_m_n_s16.c       |   26 +-
 .../arm/mve/intrinsics/vqaddq_m_n_s32.c       |   26 +-
 .../arm/mve/intrinsics/vqaddq_m_n_s8.c        |   26 +-
 .../arm/mve/intrinsics/vqaddq_m_n_u16.c       |   42 +-
 .../arm/mve/intrinsics/vqaddq_m_n_u32.c       |   42 +-
 .../arm/mve/intrinsics/vqaddq_m_n_u8.c        |   42 +-
 .../arm/mve/intrinsics/vqaddq_m_s16.c         |   26 +-
 .../arm/mve/intrinsics/vqaddq_m_s32.c         |   26 +-
 .../arm/mve/intrinsics/vqaddq_m_s8.c          |   26 +-
 .../arm/mve/intrinsics/vqaddq_m_u16.c         |   26 +-
 .../arm/mve/intrinsics/vqaddq_m_u32.c         |   26 +-
 .../arm/mve/intrinsics/vqaddq_m_u8.c          |   26 +-
 .../arm/mve/intrinsics/vqaddq_n_s16.c         |   16 +-
 .../arm/mve/intrinsics/vqaddq_n_s32.c         |   16 +-
 .../arm/mve/intrinsics/vqaddq_n_s8.c          |   16 +-
 .../arm/mve/intrinsics/vqaddq_n_u16.c         |   28 +-
 .../arm/mve/intrinsics/vqaddq_n_u32.c         |   28 +-
 .../arm/mve/intrinsics/vqaddq_n_u8.c          |   28 +-
 .../arm/mve/intrinsics/vqaddq_s16.c           |   16 +-
 .../arm/mve/intrinsics/vqaddq_s32.c           |   16 +-
 .../gcc.target/arm/mve/intrinsics/vqaddq_s8.c |   16 +-
 .../arm/mve/intrinsics/vqaddq_u16.c           |   16 +-
 .../arm/mve/intrinsics/vqaddq_u32.c           |   16 +-
 .../gcc.target/arm/mve/intrinsics/vqaddq_u8.c |   16 +-
 .../arm/mve/intrinsics/vqdmlahq_m_n_s16.c     |   34 +-
 .../arm/mve/intrinsics/vqdmlahq_m_n_s32.c     |   34 +-
 .../arm/mve/intrinsics/vqdmlahq_m_n_s8.c      |   34 +-
 .../arm/mve/intrinsics/vqdmlahq_n_s16.c       |   24 +-
 .../arm/mve/intrinsics/vqdmlahq_n_s32.c       |   24 +-
 .../arm/mve/intrinsics/vqdmlahq_n_s8.c        |   24 +-
 .../arm/mve/intrinsics/vqdmlashq_m_n_s16.c    |   34 +-
 .../arm/mve/intrinsics/vqdmlashq_m_n_s32.c    |   34 +-
 .../arm/mve/intrinsics/vqdmlashq_m_n_s8.c     |   34 +-
 .../arm/mve/intrinsics/vqdmlashq_n_s16.c      |   24 +-
 .../arm/mve/intrinsics/vqdmlashq_n_s32.c      |   24 +-
 .../arm/mve/intrinsics/vqdmlashq_n_s8.c       |   24 +-
 .../arm/mve/intrinsics/vqdmulhq_m_n_s16.c     |   26 +-
 .../arm/mve/intrinsics/vqdmulhq_m_n_s32.c     |   26 +-
 .../arm/mve/intrinsics/vqdmulhq_m_n_s8.c      |   26 +-
 .../arm/mve/intrinsics/vqdmulhq_m_s16.c       |   26 +-
 .../arm/mve/intrinsics/vqdmulhq_m_s32.c       |   26 +-
 .../arm/mve/intrinsics/vqdmulhq_m_s8.c        |   26 +-
 .../arm/mve/intrinsics/vqdmulhq_n_s16.c       |   16 +-
 .../arm/mve/intrinsics/vqdmulhq_n_s32.c       |   16 +-
 .../arm/mve/intrinsics/vqdmulhq_n_s8.c        |   16 +-
 .../arm/mve/intrinsics/vqdmulhq_s16.c         |   16 +-
 .../arm/mve/intrinsics/vqdmulhq_s32.c         |   16 +-
 .../arm/mve/intrinsics/vqdmulhq_s8.c          |   16 +-
 .../arm/mve/intrinsics/vqdmullbq_m_n_s16.c    |   26 +-
 .../arm/mve/intrinsics/vqdmullbq_m_n_s32.c    |   26 +-
 .../arm/mve/intrinsics/vqdmullbq_m_s16.c      |   26 +-
 .../arm/mve/intrinsics/vqdmullbq_m_s32.c      |   26 +-
 .../arm/mve/intrinsics/vqdmullbq_n_s16.c      |   16 +-
 .../arm/mve/intrinsics/vqdmullbq_n_s32.c      |   16 +-
 .../arm/mve/intrinsics/vqdmullbq_s16.c        |   16 +-
 .../arm/mve/intrinsics/vqdmullbq_s32.c        |   16 +-
 .../arm/mve/intrinsics/vqdmulltq_m_n_s16.c    |   26 +-
 .../arm/mve/intrinsics/vqdmulltq_m_n_s32.c    |   26 +-
 .../arm/mve/intrinsics/vqdmulltq_m_s16.c      |   26 +-
 .../arm/mve/intrinsics/vqdmulltq_m_s32.c      |   26 +-
 .../arm/mve/intrinsics/vqdmulltq_n_s16.c      |   16 +-
 .../arm/mve/intrinsics/vqdmulltq_n_s32.c      |   16 +-
 .../arm/mve/intrinsics/vqdmulltq_s16.c        |   16 +-
 .../arm/mve/intrinsics/vqdmulltq_s32.c        |   16 +-
 .../arm/mve/intrinsics/vqrdmlahq_m_n_s16.c    |   34 +-
 .../arm/mve/intrinsics/vqrdmlahq_m_n_s32.c    |   34 +-
 .../arm/mve/intrinsics/vqrdmlahq_m_n_s8.c     |   34 +-
 .../arm/mve/intrinsics/vqrdmlahq_n_s16.c      |   24 +-
 .../arm/mve/intrinsics/vqrdmlahq_n_s32.c      |   24 +-
 .../arm/mve/intrinsics/vqrdmlahq_n_s8.c       |   24 +-
 .../arm/mve/intrinsics/vqrdmlashq_m_n_s16.c   |   34 +-
 .../arm/mve/intrinsics/vqrdmlashq_m_n_s32.c   |   34 +-
 .../arm/mve/intrinsics/vqrdmlashq_m_n_s8.c    |   34 +-
 .../arm/mve/intrinsics/vqsubq_m_n_s16.c       |   26 +-
 .../arm/mve/intrinsics/vqsubq_m_n_s32.c       |   26 +-
 .../arm/mve/intrinsics/vqsubq_m_n_s8.c        |   26 +-
 .../arm/mve/intrinsics/vqsubq_m_n_u16.c       |   42 +-
 .../arm/mve/intrinsics/vqsubq_m_n_u32.c       |   42 +-
 .../arm/mve/intrinsics/vqsubq_m_n_u8.c        |   42 +-
 .../arm/mve/intrinsics/vqsubq_m_s16.c         |   26 +-
 .../arm/mve/intrinsics/vqsubq_m_s32.c         |   26 +-
 .../arm/mve/intrinsics/vqsubq_m_s8.c          |   26 +-
 .../arm/mve/intrinsics/vqsubq_m_u16.c         |   26 +-
 .../arm/mve/intrinsics/vqsubq_m_u32.c         |   26 +-
 .../arm/mve/intrinsics/vqsubq_m_u8.c          |   26 +-
 .../arm/mve/intrinsics/vqsubq_n_s16.c         |   16 +-
 .../arm/mve/intrinsics/vqsubq_n_s32.c         |   16 +-
 .../arm/mve/intrinsics/vqsubq_n_s8.c          |   16 +-
 .../arm/mve/intrinsics/vqsubq_n_u16.c         |   28 +-
 .../arm/mve/intrinsics/vqsubq_n_u32.c         |   28 +-
 .../arm/mve/intrinsics/vqsubq_n_u8.c          |   28 +-
 .../arm/mve/intrinsics/vqsubq_s16.c           |   16 +-
 .../arm/mve/intrinsics/vqsubq_s32.c           |   16 +-
 .../gcc.target/arm/mve/intrinsics/vqsubq_s8.c |   16 +-
 .../arm/mve/intrinsics/vqsubq_u16.c           |   16 +-
 .../arm/mve/intrinsics/vqsubq_u32.c           |   16 +-
 .../gcc.target/arm/mve/intrinsics/vqsubq_u8.c |   16 +-
 .../arm/mve/intrinsics/vrmlaldavhaq_p_s32.c   |   24 +-
 .../arm/mve/intrinsics/vrmlaldavhaq_p_u32.c   |   40 +-
 .../arm/mve/intrinsics/vrshlq_m_n_s16.c       |   25 +-
 .../arm/mve/intrinsics/vrshlq_m_n_s32.c       |   25 +-
 .../arm/mve/intrinsics/vrshlq_m_n_s8.c        |   25 +-
 .../arm/mve/intrinsics/vrshlq_m_n_u16.c       |   25 +-
 .../arm/mve/intrinsics/vrshlq_m_n_u32.c       |   25 +-
 .../arm/mve/intrinsics/vrshlq_m_n_u8.c        |   25 +-
 .../arm/mve/intrinsics/vrshlq_m_s16.c         |   26 +-
 .../arm/mve/intrinsics/vrshlq_m_s32.c         |   26 +-
 .../arm/mve/intrinsics/vrshlq_m_s8.c          |   26 +-
 .../arm/mve/intrinsics/vrshlq_m_u16.c         |   26 +-
 .../arm/mve/intrinsics/vrshlq_m_u32.c         |   26 +-
 .../arm/mve/intrinsics/vrshlq_m_u8.c          |   26 +-
 .../arm/mve/intrinsics/vrshlq_n_s16.c         |   16 +-
 .../arm/mve/intrinsics/vrshlq_n_s32.c         |   16 +-
 .../arm/mve/intrinsics/vrshlq_n_s8.c          |   16 +-
 .../arm/mve/intrinsics/vrshlq_n_u16.c         |   16 +-
 .../arm/mve/intrinsics/vrshlq_n_u32.c         |   16 +-
 .../arm/mve/intrinsics/vrshlq_n_u8.c          |   16 +-
 .../arm/mve/intrinsics/vrshlq_s16.c           |   16 +-
 .../arm/mve/intrinsics/vrshlq_s32.c           |   16 +-
 .../gcc.target/arm/mve/intrinsics/vrshlq_s8.c |   16 +-
 .../arm/mve/intrinsics/vrshlq_u16.c           |   16 +-
 .../arm/mve/intrinsics/vrshlq_u32.c           |   16 +-
 .../gcc.target/arm/mve/intrinsics/vrshlq_u8.c |   16 +-
 .../arm/mve/intrinsics/vrshlq_x_s16.c         |   25 +-
 .../arm/mve/intrinsics/vrshlq_x_s32.c         |   25 +-
 .../arm/mve/intrinsics/vrshlq_x_s8.c          |   25 +-
 .../arm/mve/intrinsics/vrshlq_x_u16.c         |   25 +-
 .../arm/mve/intrinsics/vrshlq_x_u32.c         |   25 +-
 .../arm/mve/intrinsics/vrshlq_x_u8.c          |   25 +-
 .../arm/mve/intrinsics/vsetq_lane_f16.c       |   36 +-
 .../arm/mve/intrinsics/vsetq_lane_f32.c       |   36 +-
 .../arm/mve/intrinsics/vsetq_lane_s16.c       |   24 +-
 .../arm/mve/intrinsics/vsetq_lane_s32.c       |   24 +-
 .../arm/mve/intrinsics/vsetq_lane_s64.c       |   27 +-
 .../arm/mve/intrinsics/vsetq_lane_s8.c        |   24 +-
 .../arm/mve/intrinsics/vsetq_lane_u16.c       |   36 +-
 .../arm/mve/intrinsics/vsetq_lane_u32.c       |   36 +-
 .../arm/mve/intrinsics/vsetq_lane_u64.c       |   39 +-
 .../arm/mve/intrinsics/vsetq_lane_u8.c        |   36 +-
 .../gcc.target/arm/mve/intrinsics/vsubq_f16.c |   16 +-
 .../gcc.target/arm/mve/intrinsics/vsubq_f32.c |   16 +-
 .../arm/mve/intrinsics/vsubq_m_f16.c          |   26 +-
 .../arm/mve/intrinsics/vsubq_m_f32.c          |   26 +-
 .../arm/mve/intrinsics/vsubq_m_n_f16.c        |   42 +-
 .../arm/mve/intrinsics/vsubq_m_n_f32.c        |   42 +-
 .../arm/mve/intrinsics/vsubq_m_n_s16.c        |   26 +-
 .../arm/mve/intrinsics/vsubq_m_n_s32.c        |   26 +-
 .../arm/mve/intrinsics/vsubq_m_n_s8.c         |   26 +-
 .../arm/mve/intrinsics/vsubq_m_n_u16.c        |   42 +-
 .../arm/mve/intrinsics/vsubq_m_n_u32.c        |   42 +-
 .../arm/mve/intrinsics/vsubq_m_n_u8.c         |   42 +-
 .../arm/mve/intrinsics/vsubq_m_s16.c          |   25 +-
 .../arm/mve/intrinsics/vsubq_m_s32.c          |   25 +-
 .../arm/mve/intrinsics/vsubq_m_s8.c           |   25 +-
 .../arm/mve/intrinsics/vsubq_m_u16.c          |   25 +-
 .../arm/mve/intrinsics/vsubq_m_u32.c          |   25 +-
 .../arm/mve/intrinsics/vsubq_m_u8.c           |   25 +-
 .../arm/mve/intrinsics/vsubq_n_f16.c          |   28 +-
 .../arm/mve/intrinsics/vsubq_n_f32.c          |   28 +-
 .../arm/mve/intrinsics/vsubq_n_s16.c          |   17 +-
 .../arm/mve/intrinsics/vsubq_n_s32.c          |   17 +-
 .../arm/mve/intrinsics/vsubq_n_s8.c           |   17 +-
 .../arm/mve/intrinsics/vsubq_n_u16.c          |   29 +-
 .../arm/mve/intrinsics/vsubq_n_u32.c          |   29 +-
 .../arm/mve/intrinsics/vsubq_n_u8.c           |   29 +-
 .../gcc.target/arm/mve/intrinsics/vsubq_s16.c |   16 +-
 .../gcc.target/arm/mve/intrinsics/vsubq_s32.c |   16 +-
 .../gcc.target/arm/mve/intrinsics/vsubq_s8.c  |   16 +-
 .../gcc.target/arm/mve/intrinsics/vsubq_u16.c |   16 +-
 .../gcc.target/arm/mve/intrinsics/vsubq_u32.c |   16 +-
 .../gcc.target/arm/mve/intrinsics/vsubq_u8.c  |   16 +-
 .../arm/mve/intrinsics/vsubq_x_f16.c          |   32 +-
 .../arm/mve/intrinsics/vsubq_x_f32.c          |   32 +-
 .../arm/mve/intrinsics/vsubq_x_n_f16.c        |   48 +-
 .../arm/mve/intrinsics/vsubq_x_n_f32.c        |   48 +-
 .../arm/mve/intrinsics/vsubq_x_n_s16.c        |   32 +-
 .../arm/mve/intrinsics/vsubq_x_n_s32.c        |   32 +-
 .../arm/mve/intrinsics/vsubq_x_n_s8.c         |   32 +-
 .../arm/mve/intrinsics/vsubq_x_n_u16.c        |   48 +-
 .../arm/mve/intrinsics/vsubq_x_n_u32.c        |   48 +-
 .../arm/mve/intrinsics/vsubq_x_n_u8.c         |   48 +-
 .../arm/mve/intrinsics/vsubq_x_s16.c          |   32 +-
 .../arm/mve/intrinsics/vsubq_x_s32.c          |   32 +-
 .../arm/mve/intrinsics/vsubq_x_s8.c           |   32 +-
 .../arm/mve/intrinsics/vsubq_x_u16.c          |   32 +-
 .../arm/mve/intrinsics/vsubq_x_u32.c          |   32 +-
 .../arm/mve/intrinsics/vsubq_x_u8.c           |   32 +-
 868 files changed, 22007 insertions(+), 3613 deletions(-)

--
2.25.1

Comments

Andrea Corallo Nov. 28, 2022, 9:20 a.m. UTC | #1

Andrea Corallo <andrea.corallo@arm.com> writes:

> Hi all,
>
> this is the first patch series about improving the current MVE
> implementation and testsuite for:
>
> - Complete intrinsic implementation and coverage (the list of intrinsics is
>   specified by [1])
> - Verifying all instructions supposedly emitted by each intrinsic
> - Verifying register usage
> - Fixing the current scan assemblers to really match the wanted mnemonics
> - Verifying no external calls are emitted
>
> This series fixes the backend where necessary.
>
> Best Regards
>
>   Andrea

Hi Kyrill,

thank for reviewing the series!

With the requested changes this is now into trunk as of f2b54e5b796.

Best Regards

  Andrea