diff mbox series

[10/11] aarch64: Make FEAT_ASMv8p2 instruction aliases always available

Message ID fbe2b3db-35fc-b276-8273-f8022d9561a0@e124511.cambridge.arm.com
State Not Applicable
Headers
Series None |

Checks

Context Check Description
snail/binutils-gdb-check fail Git am fail log

Commit Message

Andrew Carlotti Jan. 12, 2024, 1:45 a.m. UTC 
  There's no reason to disallow the aliases when the aliased instructions are
always available.  The new behaviour matches existing LLVM behaviour.
diff mbox series

Patch

diff --git a/gas/testsuite/gas/aarch64/alias-2.d b/gas/testsuite/gas/aarch64/alias-2.d
index 45ddcf5905a677ab807c9e8f7d93dd8b10bd77a1..610382b91d1a096027ef115451d7985b2ed40e61 100644
--- a/gas/testsuite/gas/aarch64/alias-2.d
+++ b/gas/testsuite/gas/aarch64/alias-2.d
@@ -1,5 +1,5 @@ 
 #objdump: -dr
-#as: -march=armv8.2-a
+#as: -march=armv8-a
 
 .*:     file format .*
 
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 95f7757e8ebaa5ca1958be212283aa17cacdcc5b..3df273c74f3af26195039a8ed23c4e6c3784b404 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -3572,7 +3572,7 @@  const struct aarch64_opcode aarch64_opcode_table[] =
   CORE_INSN ("asr", 0x13000000, 0x7f800000, bitfield, OP_ASR_IMM, OP3 (Rd, Rn, IMM), QL_SHIFT, F_ALIAS | F_P2 | F_CONV),
   CORE_INSN ("bfm", 0x33000000, 0x7f800000, bitfield, 0, OP4 (Rd, Rn, IMMR, IMMS), QL_BF, F_HAS_ALIAS | F_SF | F_N),
   CORE_INSN ("bfi", 0x33000000, 0x7f800000, bitfield, OP_BFI, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV),
-  V8_2A_INSN ("bfc", 0x330003e0, 0x7f8003e0, bitfield, OP_BFC, OP3 (Rd, IMM, WIDTH), QL_BF1, F_ALIAS | F_P2 | F_CONV),
+  CORE_INSN ("bfc", 0x330003e0, 0x7f8003e0, bitfield, OP_BFC, OP3 (Rd, IMM, WIDTH), QL_BF1, F_ALIAS | F_P2 | F_CONV),
   CORE_INSN ("bfxil", 0x33000000, 0x7f800000, bitfield, OP_BFXIL, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV),
   CORE_INSN ("ubfm", 0x53000000, 0x7f800000, bitfield, 0, OP4 (Rd, Rn, IMMR, IMMS), QL_BF, F_HAS_ALIAS | F_SF | F_N),
   CORE_INSN ("ubfiz", 0x53000000, 0x7f800000, bitfield, OP_UBFIZ, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV),
@@ -3645,7 +3645,7 @@  const struct aarch64_opcode aarch64_opcode_table[] =
   CORE_INSN ("rev16", 0x5ac00400, 0x7ffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAME, F_SF),
   CORE_INSN ("rev",   0x5ac00800, 0xfffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAMEW, 0),
   CORE_INSN ("rev",   0xdac00c00, 0xfffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAMEX, F_SF | F_HAS_ALIAS | F_P1),
-  V8_2A_INSN ("rev64", 0xdac00c00, 0xfffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAMEX, F_SF | F_ALIAS),
+  CORE_INSN ("rev64", 0xdac00c00, 0xfffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAMEX, F_SF | F_ALIAS),
   CORE_INSN ("clz",   0x5ac01000, 0x7ffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAME, F_SF),
   CORE_INSN ("cls",   0x5ac01400, 0x7ffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAME, F_SF),
   CORE_INSN ("rev32", 0xdac00800, 0xfffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAMEX, 0),