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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id b12-20020a056402278c00b004588af9ea19si5130780ede.166.2022.11.18.23.13.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Nov 2022 23:13:48 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=OgGzCY9j; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 40344385840C for ; Sat, 19 Nov 2022 07:13:47 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 40344385840C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1668842027; bh=arkgSoMhlDt74UwBzjlmPpq25qHdMxPY/EeawyU7xIo=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=OgGzCY9j5hirhAiikMGpamMnP4V6/FiODowOpgnmFGDTT33Op3BDLENmsirkHGnD8 iMXW1pK1JaW5RUESx/3FyLGXCoevws0Y5zOVLr3nlQMrjICwtyM7Rwb1It13Trm50b ZQCnolARe0xWLfAaT9LbN6Qr5fZMd6cxEMMbD2kw= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 17EE43858288 for ; Sat, 19 Nov 2022 07:11:46 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 17EE43858288 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 1DF8C300089; Sat, 19 Nov 2022 07:11:44 +0000 (UTC) To: Tsukasa OI , Jan Beulich , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [PATCH 2/2] RISC-V: Better support for long instructions Date: Sat, 19 Nov 2022 07:10:34 +0000 Message-Id: In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, KAM_LOTSOFHASH, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749907698763029591?= X-GMAIL-MSGID: =?utf-8?q?1749907698763029591?= From: Tsukasa OI Commit bb996692bd96 ("RISC-V/gas: allow generating up to 176-bit instructions with .insn") tried to start supporting long instructions but it was insufficient. 1. It heavily depended on the bignum internals (radix of 2^16), 2. It generates "value conflicts with instruction length" even if a big number instruction encoding does not exceed its expected length, 3. Because long opcode was handled separately (from struct riscv_cl_insn), some information like DWARF line number correspondence was missing and 4. On the disassembler, disassembler dump was limited up to 64-bit. For long (unknown) instructions, instruction bits are incorrectly zeroed out. To solve these problems, this commit: 1. Handles bignum (and its encodings) precisely, 2. Incorporates long opcode handling into regular struct riscv_cl_insn-handling functions. 3. Adds packet argument to support dumping instructions longer than 64-bits. gas/ChangeLog: * config/tc-riscv.c (struct riscv_cl_insn): Add long opcode field. (create_insn) Clear long opcode marker. (install_insn) Install longer opcode as well. (s_riscv_insn) Likewise. (riscv_ip_hardcode): Make big number handling stricter. Length and the value conflicts only if the bignum size exceeds the expected length. * testsuite/gas/riscv/insn.s: Add testcases such that big number handling is required. * testsuite/gas/riscv/insn.d: Likewise. * testsuite/gas/riscv/insn-na.d: Likewise. * testsuite/gas/riscv/insn-dwarf.d: Likewise. opcodes/ChangeLog: * riscv-dis.c (riscv_disassemble_insn): Print unknown instruction using the new argument packet. (riscv_disassemble_data): Add unused argument packet. (print_insn_riscv): Pass packet to the disassemble function. --- gas/config/tc-riscv.c | 50 +++++++++++++++++++++++----- gas/testsuite/gas/riscv/insn-dwarf.d | 10 +++++- gas/testsuite/gas/riscv/insn-na.d | 8 +++++ gas/testsuite/gas/riscv/insn.d | 22 ++++++++++++ gas/testsuite/gas/riscv/insn.s | 9 +++++ opcodes/riscv-dis.c | 13 +++++--- 6 files changed, 98 insertions(+), 14 deletions(-) diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 019545171f5e..98e8ea0f5f6b 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -45,6 +45,9 @@ struct riscv_cl_insn /* The encoded instruction bits. */ insn_t insn_opcode; + /* The long encoded instruction bits ([0] is non-zero if used). */ + char insn_long_opcode[RISCV_MAX_INSN_LEN]; + /* The frag that contains the instruction. */ struct frag *frag; @@ -714,6 +717,7 @@ create_insn (struct riscv_cl_insn *insn, const struct riscv_opcode *mo) { insn->insn_mo = mo; insn->insn_opcode = mo->match; + insn->insn_long_opcode[0] = 0; /* Long insn has non-zero value. */ insn->frag = NULL; insn->where = 0; insn->fixp = NULL; @@ -725,7 +729,10 @@ static void install_insn (const struct riscv_cl_insn *insn) { char *f = insn->frag->fr_literal + insn->where; - number_to_chars_littleendian (f, insn->insn_opcode, insn_length (insn)); + if (insn->insn_long_opcode[0] != 0) + memcpy (f, insn->insn_long_opcode, insn_length (insn)); + else + number_to_chars_littleendian (f, insn->insn_opcode, insn_length (insn)); } /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly @@ -3481,7 +3488,21 @@ riscv_ip_hardcode (char *str, values[num++] = (insn_t) imm_expr->X_add_number; break; case O_big: - values[num++] = generic_bignum[0]; + /* Extract lower 16-bits of a big number. */ + if (CHARS_PER_LITTLENUM == 1) + { + offsetT n = imm_expr->X_add_number; + n = n > 2 ? 2 : n; + values[num] = 0; + for (offsetT i = 0; i < n; ++i) + { + values[num] *= (insn_t) LITTLENUM_RADIX; + values[num] |= (insn_t) generic_bignum[n - i - 1]; + } + num++; + } + else + values[num++] = (insn_t) generic_bignum[0]; break; default: /* The first value isn't constant, so it should be @@ -3508,12 +3529,25 @@ riscv_ip_hardcode (char *str, if (imm_expr->X_op == O_big) { - if (bytes != imm_expr->X_add_number * CHARS_PER_LITTLENUM) + unsigned int llen = 0; + for (LITTLENUM_TYPE lval = generic_bignum[imm_expr->X_add_number - 1]; + lval != 0; llen++) + lval >>= BITS_PER_CHAR; + unsigned int repr_bytes + = (imm_expr->X_add_number - 1) * CHARS_PER_LITTLENUM + llen; + if (bytes < repr_bytes) return _("value conflicts with instruction length"); - char *f = frag_more (bytes); - for (num = 0; num < imm_expr->X_add_number; ++num) - number_to_chars_littleendian (f + num * CHARS_PER_LITTLENUM, - generic_bignum[num], CHARS_PER_LITTLENUM); + for (num = 0; num < imm_expr->X_add_number - 1; ++num) + number_to_chars_littleendian ( + ip->insn_long_opcode + num * CHARS_PER_LITTLENUM, + generic_bignum[num], + CHARS_PER_LITTLENUM); + if (llen != 0) + number_to_chars_littleendian ( + ip->insn_long_opcode + num * CHARS_PER_LITTLENUM, + generic_bignum[num], + llen); + memset(ip->insn_long_opcode + repr_bytes, 0, bytes - repr_bytes); return NULL; } @@ -4590,7 +4624,7 @@ s_riscv_insn (int x ATTRIBUTE_UNUSED) else as_bad ("%s `%s'", error.msg, error.statement); } - else if (imm_expr.X_op != O_big) + else { gas_assert (insn.insn_mo->pinfo != INSN_MACRO); append_insn (&insn, &imm_expr, imm_reloc); diff --git a/gas/testsuite/gas/riscv/insn-dwarf.d b/gas/testsuite/gas/riscv/insn-dwarf.d index 89dc8d58ff09..b8bd42dff18c 100644 --- a/gas/testsuite/gas/riscv/insn-dwarf.d +++ b/gas/testsuite/gas/riscv/insn-dwarf.d @@ -74,5 +74,13 @@ insn.s +69 +0xf6.* insn.s +70 +0xfe.* insn.s +71 +0x108.* insn.s +72 +0x114.* -insn.s +- +0x12a +insn.s +74 +0x12a.* +insn.s +75 +0x134.* +insn.s +76 +0x13e.* +insn.s +77 +0x154.* +insn.s +78 +0x16a.* +insn.s +79 +0x180.* +insn.s +80 +0x196.* +insn.s +81 +0x1ac.* +insn.s +- +0x1c2 #pass diff --git a/gas/testsuite/gas/riscv/insn-na.d b/gas/testsuite/gas/riscv/insn-na.d index be6c9f9dd66a..60024555c71f 100644 --- a/gas/testsuite/gas/riscv/insn-na.d +++ b/gas/testsuite/gas/riscv/insn-na.d @@ -73,3 +73,11 @@ Disassembly of section .text: [^:]+:[ ]+007f 0000 0000 0000 0000[ ]+\.byte[ ]+0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 [^:]+:[ ]+0000107f 00000000 00000000[ ]+\.byte[ ]+0x7f, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 [^:]+:[ ]+607f 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000[ ]+\.byte[ ]+0x7f, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +[^:]+:[ ]+007f 0000 0000 0000 8000[ ]+\.byte[ ]+0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80 +[^:]+:[ ]+007f 0000 0000 0000 8000[ ]+\.byte[ ]+0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80 +[^:]+:[ ]+607f 89ab 4567 0123 3210 7654 ba98 fedc 0000 0000 0000[ ]+\.byte[ ]+0x7f, 0x60, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +[^:]+:[ ]+607f 89ab 4567 0123 3210 7654 ba98 fedc 0000 0000 0000[ ]+\.byte[ ]+0x7f, 0x60, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +[^:]+:[ ]+607f 33cc 55aa cdef 89ab 4567 0123 3210 7654 ba98 00dc[ ]+\.byte[ ]+0x7f, 0x60, 0xcc, 0x33, 0xaa, 0x55, 0xef, 0xcd, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0x00 +[^:]+:[ ]+607f 33cc 55aa cdef 89ab 4567 0123 3210 7654 ba98 00dc[ ]+\.byte[ ]+0x7f, 0x60, 0xcc, 0x33, 0xaa, 0x55, 0xef, 0xcd, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0x00 +[^:]+:[ ]+607f 33cc 55aa cdef 89ab 4567 0123 3210 7654 ba98 fedc[ ]+\.byte[ ]+0x7f, 0x60, 0xcc, 0x33, 0xaa, 0x55, 0xef, 0xcd, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0xfe +[^:]+:[ ]+607f 33cc 55aa cdef 89ab 4567 0123 3210 7654 ba98 fedc[ ]+\.byte[ ]+0x7f, 0x60, 0xcc, 0x33, 0xaa, 0x55, 0xef, 0xcd, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0xfe diff --git a/gas/testsuite/gas/riscv/insn.d b/gas/testsuite/gas/riscv/insn.d index cf84f177af39..b02d67c5f120 100644 --- a/gas/testsuite/gas/riscv/insn.d +++ b/gas/testsuite/gas/riscv/insn.d @@ -92,3 +92,25 @@ Disassembly of section .text: [^:]+:[ ]+607f 0000 0000 0000[ ]+\.byte[ ]+0x7f, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 [^:]+:[ ]+0000 0000 0000 0000 ? [^:]+:[ ]+0000 0000 0000 ? +[^:]+:[ ]+007f 0000 0000 0000[ ]+\.byte[ ]+0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80 +[^:]+:[ ]+8000 ? +[^:]+:[ ]+007f 0000 0000 0000[ ]+\.byte[ ]+0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80 +[^:]+:[ ]+8000 ? +[^:]+:[ ]+607f 89ab 4567 0123[ ]+\.byte[ ]+0x7f, 0x60, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +[^:]+:[ ]+3210 7654 ba98 fedc ? +[^:]+:[ ]+0000 0000 0000 ? +[^:]+:[ ]+607f 89ab 4567 0123[ ]+\.byte[ ]+0x7f, 0x60, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +[^:]+:[ ]+3210 7654 ba98 fedc ? +[^:]+:[ ]+0000 0000 0000 ? +[^:]+:[ ]+607f 33cc 55aa cdef[ ]+\.byte[ ]+0x7f, 0x60, 0xcc, 0x33, 0xaa, 0x55, 0xef, 0xcd, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0x00 +[^:]+:[ ]+89ab 4567 0123 3210 ? +[^:]+:[ ]+7654 ba98 00dc ? +[^:]+:[ ]+607f 33cc 55aa cdef[ ]+\.byte[ ]+0x7f, 0x60, 0xcc, 0x33, 0xaa, 0x55, 0xef, 0xcd, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0x00 +[^:]+:[ ]+89ab 4567 0123 3210 ? +[^:]+:[ ]+7654 ba98 00dc ? +[^:]+:[ ]+607f 33cc 55aa cdef[ ]+\.byte[ ]+0x7f, 0x60, 0xcc, 0x33, 0xaa, 0x55, 0xef, 0xcd, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0xfe +[^:]+:[ ]+89ab 4567 0123 3210 ? +[^:]+:[ ]+7654 ba98 fedc ? +[^:]+:[ ]+607f 33cc 55aa cdef[ ]+\.byte[ ]+0x7f, 0x60, 0xcc, 0x33, 0xaa, 0x55, 0xef, 0xcd, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0xfe +[^:]+:[ ]+89ab 4567 0123 3210 ? +[^:]+:[ ]+7654 ba98 fedc ? diff --git a/gas/testsuite/gas/riscv/insn.s b/gas/testsuite/gas/riscv/insn.s index 94f62fe5672e..48db59b14e88 100644 --- a/gas/testsuite/gas/riscv/insn.s +++ b/gas/testsuite/gas/riscv/insn.s @@ -70,3 +70,12 @@ target: .insn 10, 0x007f .insn 12, 0x107f .insn 22, 0x607f + + .insn 0x8000000000000000007f + .insn 10, 0x8000000000000000007f + .insn 0x000000000000fedcba98765432100123456789ab607f + .insn 22, 0x000000000000fedcba98765432100123456789ab607f + .insn 0x00dcba98765432100123456789abcdef55aa33cc607f + .insn 22, 0x00dcba98765432100123456789abcdef55aa33cc607f + .insn 0xfedcba98765432100123456789abcdef55aa33cc607f + .insn 22, 0xfedcba98765432100123456789abcdef55aa33cc607f diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 3a31647a2f80..59ebbaf13417 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -641,7 +641,10 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info this is little-endian code. */ static int -riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info) +riscv_disassemble_insn (bfd_vma memaddr, + insn_t word, + const bfd_byte *packet, + disassemble_info *info) { const struct riscv_opcode *op; static bool init = false; @@ -806,8 +809,7 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info) ", "); (*info->fprintf_styled_func) (info->stream, dis_style_immediate, "0x%02x", - (unsigned int) (word & 0xff)); - word >>= 8; + (unsigned int) (*packet++)); } } break; @@ -983,6 +985,7 @@ riscv_data_length (bfd_vma memaddr, static int riscv_disassemble_data (bfd_vma memaddr ATTRIBUTE_UNUSED, insn_t data, + const bfd_byte *packet ATTRIBUTE_UNUSED, disassemble_info *info) { info->display_endian = info->endian; @@ -1037,7 +1040,7 @@ print_insn_riscv (bfd_vma memaddr, struct disassemble_info *info) bfd_vma dump_size; int status; enum riscv_seg_mstate mstate; - int (*riscv_disassembler) (bfd_vma, insn_t, struct disassemble_info *); + int (*riscv_disassembler) (bfd_vma, insn_t, const bfd_byte*, struct disassemble_info *); if (info->disassembler_options != NULL) { @@ -1081,7 +1084,7 @@ print_insn_riscv (bfd_vma memaddr, struct disassemble_info *info) } insn = (insn_t) bfd_get_bits (packet, dump_size * 8, false); - return (*riscv_disassembler) (memaddr, insn, info); + return (*riscv_disassembler) (memaddr, insn, packet, info); } disassembler_ftype