From patchwork Sun Nov 20 01:08:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 23361 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp927846wrr; Sat, 19 Nov 2022 17:09:41 -0800 (PST) X-Google-Smtp-Source: AA0mqf40npDvHcq8fsLPFQUFAGr7vK5b9rfaszClzt5wB8NALitlnHZUbf2vlNSZM16qZvQ+Phy7 X-Received: by 2002:a17:906:85cc:b0:781:ee12:814 with SMTP id i12-20020a17090685cc00b00781ee120814mr10832624ejy.63.1668906581696; Sat, 19 Nov 2022 17:09:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668906581; cv=none; d=google.com; s=arc-20160816; b=K5u0pOIvRDy1vfnWAWOt/dRIuVlMTzGU+aAmdtVKOXUNgEdfMwZjmzUQYZMRK6kITT D2rleXvPE9LU7lELZi9VMXtsUuPOc3ZKSAnOYi6vQpHW1cEqYcq6huP/JYbiKgXmH0x0 qSWg70t60edLCNUTvjQep9RHyn/qtmKlUplJCMxizl8h7TL0ycI+f/GoqOUnAtnZ5lG/ FOyhGBJeCNE9TSP6c2IaRJS4W96MDn2800NtHuwjF6e8FY7MOR2cwxx5M/DaAcMD1CIE M05PQ8L9HcpSNe02228yWffsLCfbn14V0dqEwvL3Wk8j7AFVbZVtm7h3Jvs3Wt2zU1rT a9cQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=bqVKxVIxyP+rGuYBtRFvslLlo3JqQ7uHZKUZGeif3og=; b=GQWJ4plmi1pC5I8VOzzOG4g8fgIugHAQHeEGqfnNdaVJngoyx/tvSEiF8WgVMDR816 OwvWrqSUWsCrgOIBsAMByNWfjKhvVMDCSEAe+VlAadWuTo6AmgJqGVOqNAH92TfkKBV/ L9xwrtXO6DoD/Qu+SHuj7B1aGRKxYjZOBOCdZw+euHLQg+i47v+4RkJL/MFjNwFLlYuB NuoLSVMPqY//ZBohvaHL1jR0QyvuCZcbu2e29084nk8o3OXEOp5FmtwnbAKRwZ0Q7tNF BcYTbOlrKyfoDg1q9n7Wg9anSoxISbTuxYzLhHwlmRp0fpvQynhVkt4d4zntoEGQTaUT hzYg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b="sxJ/x8bW"; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id hb44-20020a170907162c00b007b2b5ab155esi4043878ejc.363.2022.11.19.17.09.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Nov 2022 17:09:41 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b="sxJ/x8bW"; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8012F3889E2B for ; Sun, 20 Nov 2022 01:09:40 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8012F3889E2B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1668906580; bh=bqVKxVIxyP+rGuYBtRFvslLlo3JqQ7uHZKUZGeif3og=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=sxJ/x8bWaGF3yd06euzesEkp5vna/NI68Fsq4qlxM8V1iaVFls9JSGclhU4WOJbf6 K8+iF/XWZ8CL0UU3TKvYfgZs2v/MO7lBUWcbUsmHhfkXh2PRKkCHwqPg/J2AVFbVRj phaiNWn3Hc2toRikToLIQrPxYyyx3C+LYBYCzwNE= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 470333889E3B for ; Sun, 20 Nov 2022 01:09:13 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 470333889E3B Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 9A2DC300089; Sun, 20 Nov 2022 01:09:11 +0000 (UTC) To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [PATCH 2/3] RISC-V: Fallback on faster hash table Date: Sun, 20 Nov 2022 01:08:41 +0000 Message-Id: In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749975387644190681?= X-GMAIL-MSGID: =?utf-8?q?1749975387644190681?= From: Tsukasa OI Although it does not have a problem on current GNU Binutils implementation, if the custom vendor implements an instruction which spans across multiple major opcodes (e.g. uses both CUSTOM_0 and CUSTOM_1 in a *single* custom instruction), the original assumption of the sorted hash table breaks. In this case, this commit enables the fallback mode to disable all optimizations except filtering macros out. Note that, if a such instruction (that disables this disassembler optimization) is upstreamed to Binutils, a separate solution will be required to avoid major performance degradation when such instruction is not used. The intent of this commit is to make a room for custom vendors to implement such instructions in *their* tree without causing disassembler problems. opcodes/ChangeLog: * riscv-dis.c (is_riscv_hash_fallback) New. (build_riscv_opcodes_hash_table): If an instruction spans across multiple major opcodes, enable fallback mode and disable sorting. (riscv_disassemble_insn): If the fallback mode is enabled, scan through all instructions instead of scanning only instruction entries matching the hash value. --- opcodes/riscv-dis.c | 31 ++++++++++++++++++++++++++----- 1 file changed, 26 insertions(+), 5 deletions(-) diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index a4a74e5733a5..197f6a31d439 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -838,6 +838,9 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info static const struct riscv_opcode **riscv_hash[OP_HASH_LEN + 1]; static const struct riscv_opcode **riscv_opcodes_sorted; +/* Whether the fallback should be used. */ +static bool is_riscv_hash_fallback = false; + /* Compare two riscv_opcode* objects to sort by hash index. */ static int @@ -868,15 +871,25 @@ build_riscv_opcodes_hash_table (void) /* Sort riscv_opcodes entry pointers (except macros). */ for (op = riscv_opcodes; op->name; op++) - if (op->pinfo != INSN_MACRO) + { + if (op->pinfo == INSN_MACRO) + continue; len++; + if (is_riscv_hash_fallback) + continue; + if (OP_HASH_IDX (op->match) < OP_MASK_OP2 + ? (op->mask & OP_MASK_OP2) != OP_MASK_OP2 + : (op->mask & OP_MASK_OP) != OP_MASK_OP) + is_riscv_hash_fallback = true; + } riscv_opcodes_sorted = xcalloc (len, sizeof (struct riscv_opcode *)); pop_end = riscv_opcodes_sorted; for (op = riscv_opcodes; op->name; op++) if (op->pinfo != INSN_MACRO) *pop_end++ = op; - qsort (riscv_opcodes_sorted, len, sizeof (struct riscv_opcode *), - compare_opcodes); + if (!is_riscv_hash_fallback) + qsort (riscv_opcodes_sorted, len, sizeof (struct riscv_opcode *), + compare_opcodes); /* Initialize faster hash table. */ pop = riscv_opcodes_sorted; @@ -919,8 +932,16 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info) info->target2 = 0; matched_op = NULL; - pop = riscv_hash[OP_HASH_IDX (word)]; - pop_end = riscv_hash[OP_HASH_IDX (word) + 1]; + if (!is_riscv_hash_fallback) + { + pop = riscv_hash[OP_HASH_IDX (word)]; + pop_end = riscv_hash[OP_HASH_IDX (word) + 1]; + } + else + { + pop = riscv_hash[0]; + pop_end = riscv_hash[OP_HASH_LEN]; + } for (; pop != pop_end; pop++) { op = *pop;