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[v4,7/8] RISC-V: Make alias instructions aliases

Message ID e5d45f2c8d1bb5b2d9adbfa117a3fc7d32afd6c9.1668737241.git.research_trasio@irq.a4lg.com
State Accepted
Headers
Series RISC-V: Various opcode tidying (batch 1) |

Checks

Context Check Description
snail/binutils-gdb-check success Github commit url

Commit Message

Tsukasa OI Nov. 18, 2022, 2:07 a.m. UTC 
  This commit makes following alias instruction real aliases.

-   scall   (an alias of "ecall")
-   fmv.x.s (an alias of "fmv.x.w")
-   fmv.s.x (an alias of "fmv.w.x")

opcodes/ChangeLog:

	* riscv-opc.c (riscv_opcodes): Make alias instructions aliases.
---
 opcodes/riscv-opc.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)
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Patch

diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 459bf5dc5f64..77ea6f64ea05 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -475,7 +475,7 @@  const struct riscv_opcode riscv_opcodes[] =
 {"rdinstreth", 32, INSN_CLASS_I, "d",         MATCH_RDINSTRETH, MASK_RDINSTRETH, match_opcode, INSN_ALIAS },
 {"rdtimeh",    32, INSN_CLASS_I, "d",         MATCH_RDTIMEH, MASK_RDTIMEH, match_opcode, INSN_ALIAS },
 {"ecall",       0, INSN_CLASS_I, "",          MATCH_ECALL, MASK_ECALL, match_opcode, 0 },
-{"scall",       0, INSN_CLASS_I, "",          MATCH_ECALL, MASK_ECALL, match_opcode, 0 },
+{"scall",       0, INSN_CLASS_I, "",          MATCH_ECALL, MASK_ECALL, match_opcode, INSN_ALIAS },
 {"xor",         0, INSN_CLASS_I, "d,s,j",     MATCH_XORI, MASK_XORI, match_opcode, INSN_ALIAS },
 {"xor",         0, INSN_CLASS_C, "Cs,Cw,Ct",  MATCH_C_XOR, MASK_C_XOR, match_opcode, INSN_ALIAS },
 {"xor",         0, INSN_CLASS_C, "Cs,Ct,Cw",  MATCH_C_XOR, MASK_C_XOR, match_opcode, INSN_ALIAS },
@@ -710,8 +710,8 @@  const struct riscv_opcode riscv_opcodes[] =
 {"fsw",        0, INSN_CLASS_F,   "T,A,s",     0, (int) M_FSW, match_never, INSN_MACRO },
 {"fmv.x.w",    0, INSN_CLASS_F,   "d,S",       MATCH_FMV_X_W, MASK_FMV_X_W, match_opcode, 0 },
 {"fmv.w.x",    0, INSN_CLASS_F,   "D,s",       MATCH_FMV_W_X, MASK_FMV_W_X, match_opcode, 0 },
-{"fmv.x.s",    0, INSN_CLASS_F,   "d,S",       MATCH_FMV_X_W, MASK_FMV_X_W, match_opcode, 0 },
-{"fmv.s.x",    0, INSN_CLASS_F,   "D,s",       MATCH_FMV_W_X, MASK_FMV_W_X, match_opcode, 0 },
+{"fmv.x.s",    0, INSN_CLASS_F,   "d,S",       MATCH_FMV_X_W, MASK_FMV_X_W, match_opcode, INSN_ALIAS },
+{"fmv.s.x",    0, INSN_CLASS_F,   "D,s",       MATCH_FMV_W_X, MASK_FMV_W_X, match_opcode, INSN_ALIAS },
 {"fmv.s",      0, INSN_CLASS_F_INX,   "D,U",       MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS },
 {"fneg.s",     0, INSN_CLASS_F_INX,   "D,U",       MATCH_FSGNJN_S, MASK_FSGNJN_S, match_rs1_eq_rs2, INSN_ALIAS },
 {"fabs.s",     0, INSN_CLASS_F_INX,   "D,U",       MATCH_FSGNJX_S, MASK_FSGNJX_S, match_rs1_eq_rs2, INSN_ALIAS },