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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id wv2-20020a170907080200b0078dc3cb8b48si18504124ejb.625.2022.10.20.02.39.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Oct 2022 02:39:32 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=iu5AtDYC; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 75B5D385086F for ; Thu, 20 Oct 2022 09:32:44 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 75B5D385086F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1666258364; bh=49IUbsfcxVS5X7UmOx7WcoTHJppV20TW+OE+Os7D8Fk=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=iu5AtDYCUBTCNMWzkr4cH3PaSGfzh10z5k1WM6ttExD7ENOD+lAFiazwzOGj3135f gJ6BuotzGNg2JUcyNd6ZrpdMEWF8zk6YRSTgIUf0uRDwqbG83R65NJBUQjOhXuXkxu EZE/X530spKUMGH5LhOeDfNyt3PZPU5bQWEF6Cu0= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id E69AA3885C19 for ; Thu, 20 Oct 2022 09:29:26 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org E69AA3885C19 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 4865E300089; Thu, 20 Oct 2022 09:29:25 +0000 (UTC) To: Tsukasa OI , Andrew Burgess , Mike Frysinger , Nick Clifton Subject: [PATCH 16/40] sim/lm32: fix some missing function declaration warnings Date: Thu, 20 Oct 2022 09:26:02 +0000 Message-Id: In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Cc: binutils@sourceware.org Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747198958746701766?= X-GMAIL-MSGID: =?utf-8?q?1747198958746701766?= From: Andrew Burgess In the lm32 simulator, I was seeing some warnings about missing function declarations. The lm32 simulator has a weird header structure, in order to pull in the full cpu.h header we need to define WANT_CPU_LM32BF. This is done in some files, but not in others. Critically, it's not done in some files that then use functions declared in cpu.h In this commit I added the missing #define so that the full cpu.h can be included. After doing this there are still a few functions that are used undeclared, these functions appear to be missing any declarations at all, so I've added some to cpu.h. With this done all the warnings when compiling lm32 are resolved for both gcc and clang, so I've removed the SIM_WERROR_CFLAGS line from Makefile.in, this allows lm32 to build with -Werror. --- sim/lm32/Makefile.in | 3 --- sim/lm32/cpu.h | 11 +++++++++++ sim/lm32/dv-lm32cpu.c | 3 +++ sim/lm32/user.c | 3 +++ 4 files changed, 17 insertions(+), 3 deletions(-) diff --git a/sim/lm32/Makefile.in b/sim/lm32/Makefile.in index d827b711d45..db15bef47a7 100644 --- a/sim/lm32/Makefile.in +++ b/sim/lm32/Makefile.in @@ -24,9 +24,6 @@ SIM_EXTRA_DEPS = $(CGEN_INCLUDE_DEPS) $(srcdir)/../../opcodes/lm32-desc.h \ SIM_EXTRA_CLEAN = lm32-clean -# Some modules don't build cleanly yet. -dv-lm32cpu.o mloop.o sem.o traps.o user.o: SIM_WERROR_CFLAGS = - ## COMMON_POST_CONFIG_FRAG arch = lm32 diff --git a/sim/lm32/cpu.h b/sim/lm32/cpu.h index 05b98be8cf1..d025065f2ba 100644 --- a/sim/lm32/cpu.h +++ b/sim/lm32/cpu.h @@ -163,6 +163,17 @@ struct scache { struct argbuf argbuf; }; +/* From traps.c. */ +extern USI lm32bf_b_insn (SIM_CPU * current_cpu, USI r0, USI f_r0); +extern USI lm32bf_divu_insn (SIM_CPU * current_cpu, IADDR pc, USI r0, USI r1, USI r2); +extern USI lm32bf_modu_insn (SIM_CPU * current_cpu, IADDR pc, USI r0, USI r1, USI r2); +extern void lm32bf_wcsr_insn (SIM_CPU * current_cpu, USI f_csr, USI r1); +extern USI lm32bf_break_insn (SIM_CPU * current_cpu, IADDR pc); +extern USI lm32bf_scall_insn (SIM_CPU * current_cpu, IADDR pc); + +/* From user.c. */ +extern UINT lm32bf_user_insn (SIM_CPU * current_cpu, INT r0, INT r1, UINT imm); + /* Macros to simplify extraction, reading and semantic code. These define and assign the local vars that contain the insn's fields. */ diff --git a/sim/lm32/dv-lm32cpu.c b/sim/lm32/dv-lm32cpu.c index b97580e80a3..15a08eee815 100644 --- a/sim/lm32/dv-lm32cpu.c +++ b/sim/lm32/dv-lm32cpu.c @@ -18,6 +18,9 @@ You should have received a copy of the GNU General Public License along with this program. If not, see . */ +#define WANT_CPU lm32bf +#define WANT_CPU_LM32BF + /* This must come before any other includes. */ #include "defs.h" diff --git a/sim/lm32/user.c b/sim/lm32/user.c index 3cc21a208ee..d301d482c1b 100644 --- a/sim/lm32/user.c +++ b/sim/lm32/user.c @@ -21,6 +21,9 @@ /* This must come before any other includes. */ #include "defs.h" +#define WANT_CPU lm32bf +#define WANT_CPU_LM32BF + #include "sim-main.h" /* Handle user defined instructions. */