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[8.43.85.97]) by mx.google.com with ESMTPS id s12-20020a05640217cc00b00458d2bdcb30si11663164edy.96.2022.10.06.02.56.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Oct 2022 02:56:57 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=Nixziy5X; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5B142384BC3A for ; Thu, 6 Oct 2022 09:56:56 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 5B142384BC3A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1665050216; bh=1C1v2VA1s9Z0h0XEHh5iunC0k8IzNO4SWx8cSZo//+k=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=Nixziy5XPZJyyjfEzCsfwDxSRujXAVP5gz8suz+DaFanFLdhC7ckk2uAGC+XsqAbb RGNt6hsbhrzRAGrzS/zHK7rmX0qUbz83P8zgmdNSSXtiHmsS4hQ9EP5wkXcBRP2t/j gPYCF9Xyn1FKTSszrxYdfMQOgUnbfNZIWKb6gfv8= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id CA0EA384D15E for ; Thu, 6 Oct 2022 09:56:46 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org CA0EA384D15E Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 275A9300089; Thu, 6 Oct 2022 09:56:45 +0000 (UTC) To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Subject: [PATCH v3 1/2] RISC-V: Fallback for instructions longer than 64b Date: Thu, 6 Oct 2022 09:56:30 +0000 Message-Id: In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Cc: binutils@sourceware.org Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1745911805079942387?= X-GMAIL-MSGID: =?utf-8?q?1745931697090394723?= We don't support instructions longer than 64-bits yet. Still, we can modify validate_riscv_insn function to prevent unexpected behavior by limiting the "length" of an instruction to 64-bit (or less). gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): Fix function description comment based on current spec. Limit instruction length up to 64-bit for now. Make sure that required_bits does not corrupt even if unsigned long long is longer than 64-bit. --- gas/config/tc-riscv.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 22385d1baa0..41d6dfc6062 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -1109,7 +1109,8 @@ arg_lookup (char **s, const char *const *array, size_t size, unsigned *regnop) /* For consistency checking, verify that all bits are specified either by the match/mask part of the instruction definition, or by the - operand list. The `length` could be 0, 4 or 8, 0 for auto detection. */ + operand list. The `length` could be the actual instruction length or + 0 for auto-detection. */ static bool validate_riscv_insn (const struct riscv_opcode *opc, int length) @@ -1120,11 +1121,13 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length) insn_t required_bits; if (length == 0) - insn_width = 8 * riscv_insn_length (opc->match); - else - insn_width = 8 * length; + length = riscv_insn_length (opc->match); + /* We don't support instructions longer than 64-bits yet. */ + if (length > 8) + length = 8; + insn_width = 8 * length; - required_bits = ~0ULL >> (64 - insn_width); + required_bits = ((insn_t)~0ULL) >> (64 - insn_width); if ((used_bits & opc->match) != (opc->match & required_bits)) {