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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id s5-20020a170906500500b00781d302d5e9si6257826ejj.166.2022.10.08.22.10.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Oct 2022 22:10:01 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=FRgmc5KH; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 191413854833 for ; Sun, 9 Oct 2022 05:10:00 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 191413854833 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1665292200; bh=lhjTkO4GkTqmHpUFGheS+gxP5oebgO6GR0PZ68GbXCw=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=FRgmc5KHJUb+zKmQ+drA4ngIcxXEpC+YZO/iEkSk3ewU5qh4oOOt1r9kPeTLQSJEJ /t0nILa92MlO7nuvUysCDlB9izbkvVvpBrlW4w8wvtNSjK0AFGhTBvNLdw7PSzJmMU nxkmOUeLaMXY96JRObcyGDUhuXs5vjVFgM/bxOds= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 583C93858C83 for ; Sun, 9 Oct 2022 05:09:51 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 583C93858C83 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 49D5C300089; Sun, 9 Oct 2022 05:09:48 +0000 (UTC) To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Subject: [PATCH] RISC-V: Move certain arrays to riscv-opc.c Date: Sun, 9 Oct 2022 05:09:22 +0000 Message-Id: Mime-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Cc: binutils@sourceware.org Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1746185435421949625?= X-GMAIL-MSGID: =?utf-8?q?1746185435421949625?= This is a part of small tidying (declare tables in riscv-opc.c). include/ChangeLog: * opcode/riscv.h (riscv_rm, riscv_pred_succ): Move declarations to opcodes/riscv-opc.c. New non-static definitions. opcodes/ChangeLog: * riscv-opc.c (riscv_rm, riscv_pred_succ): Move from include/opcode/riscv.h. Add description. --- include/opcode/riscv.h | 13 ++----------- opcodes/riscv-opc.c | 13 +++++++++++++ 2 files changed, 15 insertions(+), 11 deletions(-) base-commit: c10a862f17847bc9c50d680c87b87dc51ae4b95e diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index f173a2eca25..dddabfdd415 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -46,17 +46,6 @@ static inline unsigned int riscv_insn_length (insn_t insn) return 2; } -static const char * const riscv_rm[8] = -{ - "rne", "rtz", "rdn", "rup", "rmm", 0, 0, "dyn" -}; - -static const char * const riscv_pred_succ[16] = -{ - 0, "w", "r", "rw", "o", "ow", "or", "orw", - "i", "iw", "ir", "irw", "io", "iow", "ior", "iorw" -}; - #define RVC_JUMP_BITS 11 #define RVC_JUMP_REACH ((1ULL << RVC_JUMP_BITS) * RISCV_JUMP_ALIGN) @@ -555,6 +544,8 @@ extern const char * const riscv_gpr_names_numeric[NGPR]; extern const char * const riscv_gpr_names_abi[NGPR]; extern const char * const riscv_fpr_names_numeric[NFPR]; extern const char * const riscv_fpr_names_abi[NFPR]; +extern const char * const riscv_rm[8]; +extern const char * const riscv_pred_succ[16]; extern const char * const riscv_vecr_names_numeric[NVECR]; extern const char * const riscv_vecm_names_numeric[NVECM]; extern const char * const riscv_vsew[8]; diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 11bb87d7eaa..04acc8470be 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -58,6 +58,19 @@ const char * const riscv_fpr_names_abi[NFPR] = "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11" }; +/* Rounding modes. */ +const char * const riscv_rm[8] = +{ + "rne", "rtz", "rdn", "rup", "rmm", 0, 0, "dyn" +}; + +/* FENCE: predecessor/successor sets. */ +const char * const riscv_pred_succ[16] = +{ + 0, "w", "r", "rw", "o", "ow", "or", "orw", + "i", "iw", "ir", "irw", "io", "iow", "ior", "iorw" +}; + /* RVV registers. */ const char * const riscv_vecr_names_numeric[NVECR] = {