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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id hg3-20020a1709072cc300b0078d7790fefdsi2752023ejc.927.2022.10.07.21.34.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Oct 2022 21:34:51 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=WBV0urqk; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 046EF38A8145 for ; Sat, 8 Oct 2022 04:34:50 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 046EF38A8145 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1665203690; bh=rUVkEJj6YIuobHhLQI1Akjf+m4CBHT+E6jEUBZZGeLM=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=WBV0urqktQpqPQ/ipLT3wjIUM+OEpcivuDpQqk6fWRe2wHZ58LQv9LG6Dh95q1wgU SOWDAbcq01kmFd7eMLPdNJGIMqvds2oNC4/WnA+979kRHXU8cOrNWCraeNozJ6Bshe A5iGCg7CnXTMFAqiPwlrokZyL66/eOFloiXgKw/Y= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id 64593382F99C for ; Sat, 8 Oct 2022 04:34:41 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 64593382F99C Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id B5165300089; Sat, 8 Oct 2022 04:34:39 +0000 (UTC) To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Subject: [PATCH 1/5] opcodes/riscv-dis.c: Tidying with comments/clarity Date: Sat, 8 Oct 2022 04:34:23 +0000 Message-Id: In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Cc: binutils@sourceware.org Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1746092625991429410?= X-GMAIL-MSGID: =?utf-8?q?1746092625991429410?= Before changing the core disassembler, we take care of minor code clarity issues and improve readability. First, we need to clarify the roles of variables and code portions. opcodes/ChangeLog: * riscv-dis.c (xlen): Move before default_isa_spec. Add comment. (default_isa_spec, default_priv_spec): Add comment. (riscv_gpr_names, riscv_fpr_names): Likewise. (parse_riscv_dis_option_without_args): Likewise. (parse_riscv_dis_option, parse_riscv_dis_options): Likewise. (maybe_print_address): Likewise. (riscv_disassemble_insn): Fix comment about the Zfinx "extension". Add comment about the riscv_multi_subset_supports call. --- opcodes/riscv-dis.c | 25 +++++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 deletions(-) diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 27a6bfe2283..2d1faf26eb3 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -32,10 +32,15 @@ #include #include +/* Current XLEN for the disassembler. */ +unsigned xlen = 0; + +/* Default ISA specification version (constant as of now). */ static enum riscv_spec_class default_isa_spec = ISA_SPEC_CLASS_DRAFT - 1; -static enum riscv_spec_class default_priv_spec = PRIV_SPEC_CLASS_NONE; -unsigned xlen = 0; +/* Default privileged specification + (as specified by the ELF attributes or the `priv-spec' option). */ +static enum riscv_spec_class default_priv_spec = PRIV_SPEC_CLASS_NONE; static riscv_subset_list_t riscv_subsets; static riscv_parse_subset_t riscv_rps_dis = @@ -61,12 +66,16 @@ static int last_map_symbol = -1; static bfd_vma last_stop_offset = 0; enum riscv_seg_mstate last_map_state; +/* Register names as used by the disassembler. */ static const char * const *riscv_gpr_names; static const char * const *riscv_fpr_names; /* If set, disassemble as most general instruction. */ static int no_aliases; + +/* Set default RISC-V disassembler options. */ + static void set_default_riscv_dis_options (void) { @@ -75,6 +84,8 @@ set_default_riscv_dis_options (void) no_aliases = 0; } +/* Parse RISC-V disassembler option (without arguments). */ + static bool parse_riscv_dis_option_without_args (const char *option) { @@ -90,6 +101,8 @@ parse_riscv_dis_option_without_args (const char *option) return true; } +/* Parse RISC-V disassembler option (possibly with arguments). */ + static void parse_riscv_dis_option (const char *option) { @@ -143,6 +156,8 @@ parse_riscv_dis_option (const char *option) } } +/* Parse RISC-V disassembler options. */ + static void parse_riscv_dis_options (const char *opts_in) { @@ -170,6 +185,8 @@ arg_print (struct disassemble_info *info, unsigned long val, (*info->fprintf_styled_func) (info->stream, dis_style_text, "%s", s); } +/* If we need to print an address, set its value and state. */ + static void maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset, int wide) @@ -697,7 +714,7 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info) xlen = ehdr->e_ident[EI_CLASS] == ELFCLASS64 ? 64 : 32; } - /* If arch has ZFINX flags, use gpr for disassemble. */ + /* If arch has the Zfinx extension, replace FPR with GPR. */ if(riscv_subset_supports (&riscv_rps_dis, "zfinx")) riscv_fpr_names = riscv_gpr_names; @@ -712,7 +729,7 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info) /* Is this instruction restricted to a certain value of XLEN? */ if ((op->xlen_requirement != 0) && (op->xlen_requirement != xlen)) continue; - + /* Is this instruction supported by the current architecture? */ if (!riscv_multi_subset_supports (&riscv_rps_dis, op->insn_class)) continue;