@@ -1087,6 +1087,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
{"zhinx", "zhinxmin", check_implicit_always},
{"zhinxmin", "zfinx", check_implicit_always},
{"zfinx", "zicsr", check_implicit_always},
+ {"zisslpcfi", "zicsr", check_implicit_always},
+ {"zisslpcfi", "zimop", check_implicit_always},
{"zk", "zkn", check_implicit_always},
{"zk", "zkr", check_implicit_always},
{"zk", "zkt", check_implicit_always},
@@ -1173,6 +1175,8 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zifencei", ISA_SPEC_CLASS_20191213, 2, 0, 0 },
{"zifencei", ISA_SPEC_CLASS_20190608, 2, 0, 0 },
{"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 },
+ {"zimop", ISA_SPEC_CLASS_DRAFT, 0, 1, 0 },
+ {"zisslpcfi", ISA_SPEC_CLASS_DRAFT, 0, 1, 0 },
{"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -2318,6 +2322,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
return riscv_subset_supports (rps, "zicbop");
case INSN_CLASS_ZICBOZ:
return riscv_subset_supports (rps, "zicboz");
+ case INSN_CLASS_ZISSLPCFI:
+ return riscv_subset_supports (rps, "zisslpcfi");
case INSN_CLASS_ZICSR:
return riscv_subset_supports (rps, "zicsr");
case INSN_CLASS_ZIFENCEI:
@@ -2467,6 +2473,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return "zicbop";
case INSN_CLASS_ZICBOZ:
return "zicboz";
+ case INSN_CLASS_ZISSLPCFI:
+ return "zisslpcfi";
case INSN_CLASS_ZICSR:
return "zicsr";
case INSN_CLASS_ZIFENCEI:
@@ -67,6 +67,7 @@ enum riscv_csr_class
CSR_CLASS_I,
CSR_CLASS_I_32, /* rv32 only */
CSR_CLASS_F, /* f-ext only */
+ CSR_CLASS_ZISSLPCFI, /* Zisslpcfi only */
CSR_CLASS_ZKR, /* zkr only */
CSR_CLASS_V, /* rvv only */
CSR_CLASS_DEBUG, /* debug CSR */
@@ -1037,6 +1038,9 @@ riscv_csr_address (const char *csr_name,
case CSR_CLASS_F:
extension = "f";
break;
+ case CSR_CLASS_ZISSLPCFI:
+ extension = "zisslpcfi";
+ break;
case CSR_CLASS_ZKR:
extension = "zkr";
break;
@@ -399,6 +399,8 @@ Contents of the .* section:
DW_CFA_offset_extended_sf: r4445 \(stimecmph\) at cfa\+1396
DW_CFA_offset_extended_sf: r4685 \(vstimecmp\) at cfa\+2356
DW_CFA_offset_extended_sf: r4701 \(vstimecmph\) at cfa\+2420
+ DW_CFA_offset_extended_sf: r6144 \(lplr\) at cfa\+8192
+ DW_CFA_offset_extended_sf: r6145 \(ssp\) at cfa\+8196
DW_CFA_offset_extended_sf: r4163 \(utval\) at cfa\+268
DW_CFA_offset_extended_sf: r4419 \(stval\) at cfa\+1292
DW_CFA_offset_extended_sf: r4480 \(satp\) at cfa\+1536
@@ -400,6 +400,9 @@ _start:
.cfi_offset stimecmph, 1396
.cfi_offset vstimecmp, 2356
.cfi_offset vstimecmph, 2420
+ # Zisslpci extension
+ .cfi_offset lplr, 8192
+ .cfi_offset ssp, 8196
# dropped
.cfi_offset ubadaddr, 268 # aliases
.cfi_offset sbadaddr, 1292 # aliases
@@ -773,6 +773,10 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+24d59073[ ]+csrw[ ]+vstimecmp,a1
[ ]+[0-9a-f]+:[ ]+25d02573[ ]+csrr[ ]+a0,vstimecmph
[ ]+[0-9a-f]+:[ ]+25d59073[ ]+csrw[ ]+vstimecmph,a1
+[ ]+[0-9a-f]+:[ ]+80002573[ ]+csrr[ ]+a0,lplr
+[ ]+[0-9a-f]+:[ ]+80059073[ ]+csrw[ ]+lplr,a1
+[ ]+[0-9a-f]+:[ ]+80102573[ ]+csrr[ ]+a0,ssp
+[ ]+[0-9a-f]+:[ ]+80159073[ ]+csrw[ ]+ssp,a1
[ ]+[0-9a-f]+:[ ]+04302573[ ]+csrr[ ]+a0,utval
[ ]+[0-9a-f]+:[ ]+04359073[ ]+csrw[ ]+utval,a1
[ ]+[0-9a-f]+:[ ]+14302573[ ]+csrr[ ]+a0,stval
@@ -743,6 +743,10 @@
.*Warning: invalid CSR `vstimecmph', needs rv32i extension
.*Warning: invalid CSR `vstimecmph', needs `h' extension
.*Warning: invalid CSR `vstimecmph', needs `sstc' extension
+.*Warning: invalid CSR `lplr', needs `zisslpcfi' extension
+.*Warning: invalid CSR `lplr', needs `zisslpcfi' extension
+.*Warning: invalid CSR `ssp', needs `zisslpcfi' extension
+.*Warning: invalid CSR `ssp', needs `zisslpcfi' extension
.*Warning: invalid CSR `ubadaddr' for the privileged spec `1.10'
.*Warning: invalid CSR `ubadaddr' for the privileged spec `1.10'
.*Warning: invalid CSR `sbadaddr' for the privileged spec `1.10'
@@ -773,6 +773,10 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+24d59073[ ]+csrw[ ]+vstimecmp,a1
[ ]+[0-9a-f]+:[ ]+25d02573[ ]+csrr[ ]+a0,vstimecmph
[ ]+[0-9a-f]+:[ ]+25d59073[ ]+csrw[ ]+vstimecmph,a1
+[ ]+[0-9a-f]+:[ ]+80002573[ ]+csrr[ ]+a0,lplr
+[ ]+[0-9a-f]+:[ ]+80059073[ ]+csrw[ ]+lplr,a1
+[ ]+[0-9a-f]+:[ ]+80102573[ ]+csrr[ ]+a0,ssp
+[ ]+[0-9a-f]+:[ ]+80159073[ ]+csrw[ ]+ssp,a1
[ ]+[0-9a-f]+:[ ]+04302573[ ]+csrr[ ]+a0,utval
[ ]+[0-9a-f]+:[ ]+04359073[ ]+csrw[ ]+utval,a1
[ ]+[0-9a-f]+:[ ]+14302573[ ]+csrr[ ]+a0,stval
@@ -741,6 +741,10 @@
.*Warning: invalid CSR `vstimecmph', needs rv32i extension
.*Warning: invalid CSR `vstimecmph', needs `h' extension
.*Warning: invalid CSR `vstimecmph', needs `sstc' extension
+.*Warning: invalid CSR `lplr', needs `zisslpcfi' extension
+.*Warning: invalid CSR `lplr', needs `zisslpcfi' extension
+.*Warning: invalid CSR `ssp', needs `zisslpcfi' extension
+.*Warning: invalid CSR `ssp', needs `zisslpcfi' extension
.*Warning: invalid CSR `ubadaddr' for the privileged spec `1.11'
.*Warning: invalid CSR `ubadaddr' for the privileged spec `1.11'
.*Warning: invalid CSR `sbadaddr' for the privileged spec `1.11'
@@ -773,6 +773,10 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+24d59073[ ]+csrw[ ]+vstimecmp,a1
[ ]+[0-9a-f]+:[ ]+25d02573[ ]+csrr[ ]+a0,vstimecmph
[ ]+[0-9a-f]+:[ ]+25d59073[ ]+csrw[ ]+vstimecmph,a1
+[ ]+[0-9a-f]+:[ ]+80002573[ ]+csrr[ ]+a0,lplr
+[ ]+[0-9a-f]+:[ ]+80059073[ ]+csrw[ ]+lplr,a1
+[ ]+[0-9a-f]+:[ ]+80102573[ ]+csrr[ ]+a0,ssp
+[ ]+[0-9a-f]+:[ ]+80159073[ ]+csrw[ ]+ssp,a1
[ ]+[0-9a-f]+:[ ]+04302573[ ]+csrr[ ]+a0,0x43
[ ]+[0-9a-f]+:[ ]+04359073[ ]+csrw[ ]+0x43,a1
[ ]+[0-9a-f]+:[ ]+14302573[ ]+csrr[ ]+a0,stval
@@ -603,6 +603,10 @@
.*Warning: invalid CSR `vstimecmph', needs rv32i extension
.*Warning: invalid CSR `vstimecmph', needs `h' extension
.*Warning: invalid CSR `vstimecmph', needs `sstc' extension
+.*Warning: invalid CSR `lplr', needs `zisslpcfi' extension
+.*Warning: invalid CSR `lplr', needs `zisslpcfi' extension
+.*Warning: invalid CSR `ssp', needs `zisslpcfi' extension
+.*Warning: invalid CSR `ssp', needs `zisslpcfi' extension
.*Warning: invalid CSR `ubadaddr' for the privileged spec `1.12'
.*Warning: invalid CSR `ubadaddr' for the privileged spec `1.12'
.*Warning: invalid CSR `sbadaddr' for the privileged spec `1.12'
@@ -773,6 +773,10 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+24d59073[ ]+csrw[ ]+vstimecmp,a1
[ ]+[0-9a-f]+:[ ]+25d02573[ ]+csrr[ ]+a0,vstimecmph
[ ]+[0-9a-f]+:[ ]+25d59073[ ]+csrw[ ]+vstimecmph,a1
+[ ]+[0-9a-f]+:[ ]+80002573[ ]+csrr[ ]+a0,lplr
+[ ]+[0-9a-f]+:[ ]+80059073[ ]+csrw[ ]+lplr,a1
+[ ]+[0-9a-f]+:[ ]+80102573[ ]+csrr[ ]+a0,ssp
+[ ]+[0-9a-f]+:[ ]+80159073[ ]+csrw[ ]+ssp,a1
[ ]+[0-9a-f]+:[ ]+04302573[ ]+csrr[ ]+a0,ubadaddr
[ ]+[0-9a-f]+:[ ]+04359073[ ]+csrw[ ]+ubadaddr,a1
[ ]+[0-9a-f]+:[ ]+14302573[ ]+csrr[ ]+a0,sbadaddr
@@ -793,6 +793,10 @@
.*Warning: invalid CSR `vstimecmph', needs rv32i extension
.*Warning: invalid CSR `vstimecmph', needs `h' extension
.*Warning: invalid CSR `vstimecmph', needs `sstc' extension
+.*Warning: invalid CSR `lplr', needs `zisslpcfi' extension
+.*Warning: invalid CSR `lplr', needs `zisslpcfi' extension
+.*Warning: invalid CSR `ssp', needs `zisslpcfi' extension
+.*Warning: invalid CSR `ssp', needs `zisslpcfi' extension
.*Warning: invalid CSR `utval' for the privileged spec `1.9.1'
.*Warning: invalid CSR `utval' for the privileged spec `1.9.1'
.*Warning: invalid CSR `fflags', needs `f' extension
@@ -433,6 +433,10 @@
csr vstimecmp
csr vstimecmph
+ # Control flow integrity
+ csr lplr
+ csr ssp
+
# Supported in previous priv spec, but dropped now
csr ubadaddr # 0x043 in 1.9.1, but the value is utval since 1.10
new file mode 100644
@@ -0,0 +1,2 @@
+#as: -march=rv32i_zisslpcfi
+#error_output: zisslpcfi-fail.l
new file mode 100644
@@ -0,0 +1,19 @@
+.*: Assembler messages:
+.*: Error: illegal operands `sspush x0'
+.*: Error: illegal operands `sspop x0'
+.*: Error: illegal operands `ssamoswap x0,t1,t2'
+.*: Error: illegal operands `sschkra x0,x0'
+.*: Error: illegal operands `sschkra x1,x5'
+.*: Error: illegal operands `sschkra x31,x31'
+.*: Error: improper immediate value \(-?[0-9]+\)
+.*: Error: improper immediate value \(512\)
+.*: Error: improper immediate value \(-?[0-9]+\)
+.*: Error: improper immediate value \(512\)
+.*: Error: improper immediate value \(-?[0-9]+\)
+.*: Error: improper immediate value \(256\)
+.*: Error: improper immediate value \(-?[0-9]+\)
+.*: Error: improper immediate value \(256\)
+.*: Error: improper immediate value \(-?[0-9]+\)
+.*: Error: improper immediate value \(256\)
+.*: Error: improper immediate value \(-?[0-9]+\)
+.*: Error: improper immediate value \(256\)
new file mode 100644
@@ -0,0 +1,26 @@
+target:
+ # sspush / sspop: using x0 is not allowed.
+ sspush x0
+ sspop x0
+
+ # ssamoswap: using x0 to destination is not allowed.
+ ssamoswap x0, t1, t2
+
+ # sschkra: only "sschkra x5, x1 (or t0, ra)" is allowed.
+ sschkra x0, x0
+ sschkra x1, x5
+ sschkra x31, x31
+
+ # lp*: lplr.LL is 9-bit width, lplr.{ML,UL} are 8-bit width.
+ lpsll -1
+ lpsll 0x200
+ lpcll -1
+ lpcll 0x200
+ lpsml -1
+ lpsml 0x100
+ lpcml -1
+ lpcml 0x100
+ lpsul -1
+ lpsul 0x100
+ lpcul -1
+ lpcul 0x100
new file mode 100644
@@ -0,0 +1,3 @@
+#as: -march=rv32i
+#source: zisslpcfi.s
+#error_output: zisslpcfi-noarch.l
new file mode 100644
@@ -0,0 +1,24 @@
+.*: Assembler messages:
+.*: Error: unrecognized opcode `sspush x1', extension `zisslpcfi' required
+.*: Error: unrecognized opcode `sspush x5', extension `zisslpcfi' required
+.*: Error: unrecognized opcode `sspop x1', extension `zisslpcfi' required
+.*: Error: unrecognized opcode `sspop x5', extension `zisslpcfi' required
+.*: Error: unrecognized opcode `ssprr x0', extension `zisslpcfi' required
+.*: Error: unrecognized opcode `ssprr a0', extension `zisslpcfi' required
+.*: Error: unrecognized opcode `ssamoswap a1,a2,a3', extension `zisslpcfi' required
+.*: Error: unrecognized opcode `ssamoswap t0,a0,x0', extension `zisslpcfi' required
+.*: Error: unrecognized opcode `ssamoswap a4,x0,a5', extension `zisslpcfi' required
+.*: Error: unrecognized opcode `sschkra x5,x1', extension `zisslpcfi' required
+.*: Error: unrecognized opcode `sschkra t0,ra', extension `zisslpcfi' required
+.*: Error: unrecognized opcode `lpsll 0x000', extension `zisslpcfi' required
+.*: Error: unrecognized opcode `lpsll 0x1ff', extension `zisslpcfi' required
+.*: Error: unrecognized opcode `lpcll 0x000', extension `zisslpcfi' required
+.*: Error: unrecognized opcode `lpcll 0x1ff', extension `zisslpcfi' required
+.*: Error: unrecognized opcode `lpsml 0x00', extension `zisslpcfi' required
+.*: Error: unrecognized opcode `lpsml 0xff', extension `zisslpcfi' required
+.*: Error: unrecognized opcode `lpcml 0x00', extension `zisslpcfi' required
+.*: Error: unrecognized opcode `lpcml 0xff', extension `zisslpcfi' required
+.*: Error: unrecognized opcode `lpsul 0x00', extension `zisslpcfi' required
+.*: Error: unrecognized opcode `lpsul 0xff', extension `zisslpcfi' required
+.*: Error: unrecognized opcode `lpcul 0x00', extension `zisslpcfi' required
+.*: Error: unrecognized opcode `lpcul 0xff', extension `zisslpcfi' required
new file mode 100644
@@ -0,0 +1,31 @@
+#as: -march=rv32i_zisslpcfi
+#objdump: -d
+
+.*:[ ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+81c0c073[ ]+sspush[ ]+ra
+[ ]+[0-9a-f]+:[ ]+81c2c073[ ]+sspush[ ]+t0
+[ ]+[0-9a-f]+:[ ]+81c040f3[ ]+sspop[ ]+ra
+[ ]+[0-9a-f]+:[ ]+81c042f3[ ]+sspop[ ]+t0
+[ ]+[0-9a-f]+:[ ]+81d04073[ ]+ssprr[ ]+zero
+[ ]+[0-9a-f]+:[ ]+81d04573[ ]+ssprr[ ]+a0
+[ ]+[0-9a-f]+:[ ]+82d645f3[ ]+ssamoswap[ ]+a1,a2,a3
+[ ]+[0-9a-f]+:[ ]+820542f3[ ]+ssamoswap[ ]+t0,a0,zero
+[ ]+[0-9a-f]+:[ ]+82f04773[ ]+ssamoswap[ ]+a4,zero,a5
+[ ]+[0-9a-f]+:[ ]+8a12c073[ ]+sschkra[ ]+t0,ra
+[ ]+[0-9a-f]+:[ ]+8a12c073[ ]+sschkra[ ]+t0,ra
+[ ]+[0-9a-f]+:[ ]+82004073[ ]+lpsll[ ]+0x0
+[ ]+[0-9a-f]+:[ ]+82ffc073[ ]+lpsll[ ]+0x1ff
+[ ]+[0-9a-f]+:[ ]+83004073[ ]+lpcll[ ]+0x0
+[ ]+[0-9a-f]+:[ ]+83ffc073[ ]+lpcll[ ]+0x1ff
+[ ]+[0-9a-f]+:[ ]+86004073[ ]+lpsml[ ]+0x0
+[ ]+[0-9a-f]+:[ ]+867fc073[ ]+lpsml[ ]+0xff
+[ ]+[0-9a-f]+:[ ]+86804073[ ]+lpcml[ ]+0x0
+[ ]+[0-9a-f]+:[ ]+86ffc073[ ]+lpcml[ ]+0xff
+[ ]+[0-9a-f]+:[ ]+87004073[ ]+lpsul[ ]+0x0
+[ ]+[0-9a-f]+:[ ]+877fc073[ ]+lpsul[ ]+0xff
+[ ]+[0-9a-f]+:[ ]+87804073[ ]+lpcul[ ]+0x0
+[ ]+[0-9a-f]+:[ ]+87ffc073[ ]+lpcul[ ]+0xff
new file mode 100644
@@ -0,0 +1,26 @@
+target:
+ # Shadow stack instructions
+ sspush x1
+ sspush x5
+ sspop x1
+ sspop x5
+ ssprr x0
+ ssprr a0
+ ssamoswap a1, a2, a3
+ ssamoswap t0, a0, x0
+ ssamoswap a4, x0, a5
+ sschkra x5, x1
+ sschkra t0, ra
+ # Landing pad instructions
+ lpsll 0x000
+ lpsll 0x1ff
+ lpcll 0x000
+ lpcll 0x1ff
+ lpsml 0x00
+ lpsml 0xff
+ lpcml 0x00
+ lpcml 0xff
+ lpsul 0x00
+ lpsul 0xff
+ lpcul 0x00
+ lpcul 0xff
@@ -2113,6 +2113,29 @@
#define MASK_CBO_INVAL 0xfff07fff
#define MATCH_CBO_ZERO 0x40200f
#define MASK_CBO_ZERO 0xfff07fff
+/* Zisslpcfi instructions. */
+#define MATCH_SSPUSH 0x81c04073
+#define MASK_SSPUSH 0xfff07fff
+#define MATCH_SSPOP 0x81c04073
+#define MASK_SSPOP 0xfffff07f
+#define MATCH_SSPRR 0x81d04073
+#define MASK_SSPRR 0xfffff07f
+#define MATCH_SSAMOSWAP 0x82004073
+#define MASK_SSAMOSWAP 0xfe00707f
+#define MATCH_SSCHKRA 0x8a12c073
+#define MASK_SSCHKRA 0xffffffff
+#define MATCH_LPSLL 0x82004073
+#define MASK_LPSLL 0xff007fff
+#define MATCH_LPCLL 0x83004073
+#define MASK_LPCLL 0xff007fff
+#define MATCH_LPSML 0x86004073
+#define MASK_LPSML 0xff807fff
+#define MATCH_LPCML 0x86804073
+#define MASK_LPCML 0xff807fff
+#define MATCH_LPSUL 0x87004073
+#define MASK_LPSUL 0xff807fff
+#define MATCH_LPCUL 0x87804073
+#define MASK_LPCUL 0xff807fff
/* Zawrs intructions. */
#define MATCH_WRS_NTO 0x00d00073
#define MASK_WRS_NTO 0xffffffff
@@ -2752,6 +2775,9 @@
#define CSR_STIMECMPH 0x15d
#define CSR_VSTIMECMP 0x24d
#define CSR_VSTIMECMPH 0x25d
+/* Zisslpcfi extension CSR addresses. */
+#define CSR_LPLR 0x800 /* TENTATIVELY use custom CSR address. */
+#define CSR_SSP 0x801 /* TENTATIVELY use custom CSR address. */
/* Unprivileged Floating-Point CSR addresses. */
#define CSR_FFLAGS 0x1
#define CSR_FRM 0x2
@@ -3115,6 +3141,18 @@ DECLARE_INSN(cbo_clean, MATCH_CBO_CLEAN, MASK_CBO_CLEAN);
DECLARE_INSN(cbo_flush, MATCH_CBO_FLUSH, MASK_CBO_FLUSH);
DECLARE_INSN(cbo_inval, MATCH_CBO_INVAL, MASK_CBO_INVAL);
DECLARE_INSN(cbo_zero, MATCH_CBO_ZERO, MASK_CBO_ZERO);
+/* Zisslpcfi instructions. */
+DECLARE_INSN(sspush, MATCH_SSPUSH, MASK_SSPUSH)
+DECLARE_INSN(sspop, MATCH_SSPOP, MASK_SSPOP)
+DECLARE_INSN(ssprr, MATCH_SSPRR, MASK_SSPRR)
+DECLARE_INSN(ssamoswap, MATCH_SSAMOSWAP, MASK_SSAMOSWAP)
+DECLARE_INSN(sschkra, MATCH_SSCHKRA, MASK_SSCHKRA)
+DECLARE_INSN(lpsll, MATCH_LPSLL, MASK_LPSLL)
+DECLARE_INSN(lpcll, MATCH_LPCLL, MASK_LPCLL)
+DECLARE_INSN(lpsml, MATCH_LPSML, MASK_LPSML)
+DECLARE_INSN(lpcml, MATCH_LPCML, MASK_LPCML)
+DECLARE_INSN(lpsul, MATCH_LPSUL, MASK_LPSUL)
+DECLARE_INSN(lpcul, MATCH_LPCUL, MASK_LPCUL)
/* Zawrs instructions. */
DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO)
DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO)
@@ -3648,6 +3686,9 @@ DECLARE_CSR(utval, CSR_UTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS
DECLARE_CSR(uip, CSR_UIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P12)
DECLARE_CSR(sedeleg, CSR_SEDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P12)
DECLARE_CSR(sideleg, CSR_SIDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P12)
+/* Zisslpcfi extension CSRs. */
+DECLARE_CSR(lplr, CSR_LPLR, CSR_CLASS_ZISSLPCFI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(ssp, CSR_SSP, CSR_CLASS_ZISSLPCFI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
/* Unprivileged Floating-Point CSRs. */
DECLARE_CSR(fflags, CSR_FFLAGS, CSR_CLASS_F, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(frm, CSR_FRM, CSR_CLASS_F, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
@@ -409,6 +409,7 @@ enum riscv_insn_class
INSN_CLASS_ZICBOM,
INSN_CLASS_ZICBOP,
INSN_CLASS_ZICBOZ,
+ INSN_CLASS_ZISSLPCFI,
INSN_CLASS_H,
INSN_CLASS_XTHEADBA,
INSN_CLASS_XTHEADBB,
@@ -171,6 +171,12 @@ match_rd_nonzero (const struct riscv_opcode *op, insn_t insn)
return match_opcode (op, insn) && ((insn & MASK_RD) != 0);
}
+static int
+match_rs1_nonzero (const struct riscv_opcode *op, insn_t insn)
+{
+ return match_opcode (op, insn) && ((insn & MASK_RS1) != 0);
+}
+
static int
match_c_add (const struct riscv_opcode *op, insn_t insn)
{
@@ -935,6 +941,19 @@ const struct riscv_opcode riscv_opcodes[] =
{"cbo.inval", 0, INSN_CLASS_ZICBOM, "0(s)", MATCH_CBO_INVAL, MASK_CBO_INVAL, match_opcode, 0 },
{"cbo.zero", 0, INSN_CLASS_ZICBOZ, "0(s)", MATCH_CBO_ZERO, MASK_CBO_ZERO, match_opcode, 0 },
+/* Zisslpcfi instructions. */
+{"sspush", 0, INSN_CLASS_ZISSLPCFI, "s", MATCH_SSPUSH, MASK_SSPUSH, match_rs1_nonzero, INSN_DREF },
+{"sspop", 0, INSN_CLASS_ZISSLPCFI, "d", MATCH_SSPOP, MASK_SSPOP, match_rd_nonzero, INSN_DREF },
+{"ssprr", 0, INSN_CLASS_ZISSLPCFI, "d", MATCH_SSPRR, MASK_SSPRR, match_opcode, 0 },
+{"ssamoswap", 0, INSN_CLASS_ZISSLPCFI, "d,s,t", MATCH_SSAMOSWAP, MASK_SSAMOSWAP, match_rd_nonzero, INSN_DREF },
+{"sschkra", 0, INSN_CLASS_ZISSLPCFI, "s,t", MATCH_SSCHKRA, MASK_SSCHKRA, match_opcode, 0 },
+{"lpsll", 0, INSN_CLASS_ZISSLPCFI, "XU9@15", MATCH_LPSLL, MASK_LPSLL, match_opcode, 0 },
+{"lpcll", 0, INSN_CLASS_ZISSLPCFI, "XU9@15", MATCH_LPCLL, MASK_LPCLL, match_opcode, 0 },
+{"lpsml", 0, INSN_CLASS_ZISSLPCFI, "XU8@15", MATCH_LPSML, MASK_LPSML, match_opcode, 0 },
+{"lpcml", 0, INSN_CLASS_ZISSLPCFI, "XU8@15", MATCH_LPCML, MASK_LPCML, match_opcode, 0 },
+{"lpsul", 0, INSN_CLASS_ZISSLPCFI, "XU8@15", MATCH_LPSUL, MASK_LPSUL, match_opcode, 0 },
+{"lpcul", 0, INSN_CLASS_ZISSLPCFI, "XU8@15", MATCH_LPCUL, MASK_LPCUL, match_opcode, 0 },
+
/* Zawrs instructions. */
{"wrs.nto", 0, INSN_CLASS_ZAWRS, "", MATCH_WRS_NTO, MASK_WRS_NTO, match_opcode, 0 },
{"wrs.sto", 0, INSN_CLASS_ZAWRS, "", MATCH_WRS_STO, MASK_WRS_STO, match_opcode, 0 },