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[8.43.85.97]) by mx.google.com with ESMTPS id p11-20020a056402500b00b004587e08bc14si10050240eda.508.2022.11.14.20.33.31 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Nov 2022 20:33:31 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=s7lnFi6q; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C207E382EF37 for ; Tue, 15 Nov 2022 04:33:09 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org C207E382EF37 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1668486789; bh=ImX6KAjYk0r8k09Kxd/Bz6LCWw3w86CfinSArLU/hCk=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=s7lnFi6qtLlPHr+J2qqEAohkjwZtDtOrkQJ62n+R8wvXSqET7bUxAXbGnqLytjvHQ cqYRSiHULb7DuYSb3bp34TNTKJEw2Fj+yBIIJkSON9WlRyBpBqye5Uylb7oKnJSM23 ejD53vc60s0qKFdc3hSNMeWMsZvnhdJIx3rr2O7A= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id 9F31C3830B03 for ; Tue, 15 Nov 2022 04:33:00 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 9F31C3830B03 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id E4B30300089; Tue, 15 Nov 2022 04:32:58 +0000 (UTC) To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [PATCH v3 8/8] RISC-V: Use defined mask and match values Date: Tue, 15 Nov 2022 04:31:29 +0000 Message-Id: In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747122137656067591?= X-GMAIL-MSGID: =?utf-8?q?1749535227250675595?= This commit replaces plain constants and named values for different instruction with defined named values matching defining instruction. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Use defined mask and match macros rather than plain literals and macros for different instructions. --- opcodes/riscv-opc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 7498a078106..40713c56c63 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -347,7 +347,7 @@ const struct riscv_opcode riscv_opcodes[] = {"call", 0, INSN_CLASS_I, "c", (X_RA << OP_SH_RS1)|(X_RA << OP_SH_RD), (int) M_CALL, match_never, INSN_MACRO }, {"tail", 0, INSN_CLASS_I, "c", (X_T1 << OP_SH_RS1), (int) M_CALL, match_never, INSN_MACRO }, {"jump", 0, INSN_CLASS_I, "c,s", 0, (int) M_CALL, match_never, INSN_MACRO }, -{"nop", 0, INSN_CLASS_C, "", MATCH_C_ADDI, 0xffff, match_opcode, INSN_ALIAS }, +{"nop", 0, INSN_CLASS_C, "", MATCH_C_NOP, MASK_C_NOP, match_opcode, INSN_ALIAS }, {"nop", 0, INSN_CLASS_I, "", MATCH_ADDI, MASK_ADDI|MASK_RD|MASK_RS1|MASK_IMM, match_opcode, INSN_ALIAS }, {"lui", 0, INSN_CLASS_C, "d,Cu", MATCH_C_LUI, MASK_C_LUI, match_c_lui, INSN_ALIAS }, {"lui", 0, INSN_CLASS_I, "d,u", MATCH_LUI, MASK_LUI, match_opcode, 0 }, @@ -466,7 +466,7 @@ const struct riscv_opcode riscv_opcodes[] = {"sw", 0, INSN_CLASS_I, "t,A,s", 0, (int) M_SW, match_never, INSN_MACRO }, {"fence", 0, INSN_CLASS_I, "", MATCH_FENCE|MASK_PRED|MASK_SUCC, MASK_FENCE|MASK_RD|MASK_RS1|MASK_IMM, match_opcode, INSN_ALIAS }, {"fence", 0, INSN_CLASS_I, "P,Q", MATCH_FENCE, MASK_FENCE|MASK_RD|MASK_RS1|(MASK_IMM & ~MASK_PRED & ~MASK_SUCC), match_opcode, 0 }, -{"fence.i", 0, INSN_CLASS_ZIFENCEI, "", MATCH_FENCE_I, MASK_FENCE|MASK_RD|MASK_RS1|MASK_IMM, match_opcode, 0 }, +{"fence.i", 0, INSN_CLASS_ZIFENCEI, "", MATCH_FENCE_I, MASK_FENCE_I|MASK_RD|MASK_RS1|MASK_IMM, match_opcode, 0 }, {"fence.tso", 0, INSN_CLASS_I, "", MATCH_FENCE_TSO, MASK_FENCE_TSO|MASK_RD|MASK_RS1, match_opcode, 0 }, {"rdcycle", 0, INSN_CLASS_I, "d", MATCH_RDCYCLE, MASK_RDCYCLE, match_opcode, INSN_ALIAS }, {"rdinstret", 0, INSN_CLASS_I, "d", MATCH_RDINSTRET, MASK_RDINSTRET, match_opcode, INSN_ALIAS }, @@ -893,7 +893,7 @@ const struct riscv_opcode riscv_opcodes[] = {"c.lw", 0, INSN_CLASS_C, "Ct,Ck(Cs)", MATCH_C_LW, MASK_C_LW, match_opcode, INSN_DREF|INSN_4_BYTE }, {"c.swsp", 0, INSN_CLASS_C, "CV,CM(Cc)", MATCH_C_SWSP, MASK_C_SWSP, match_opcode, INSN_DREF|INSN_4_BYTE }, {"c.sw", 0, INSN_CLASS_C, "Ct,Ck(Cs)", MATCH_C_SW, MASK_C_SW, match_opcode, INSN_DREF|INSN_4_BYTE }, -{"c.nop", 0, INSN_CLASS_C, "", MATCH_C_ADDI, 0xffff, match_opcode, INSN_ALIAS }, +{"c.nop", 0, INSN_CLASS_C, "", MATCH_C_NOP, MASK_C_NOP, match_opcode, INSN_ALIAS }, {"c.nop", 0, INSN_CLASS_C, "Cj", MATCH_C_ADDI, MASK_C_ADDI|MASK_RD, match_opcode, INSN_ALIAS }, {"c.mv", 0, INSN_CLASS_C, "d,CV", MATCH_C_MV, MASK_C_MV, match_c_add_with_hint, 0 }, {"c.lui", 0, INSN_CLASS_C, "d,Cu", MATCH_C_LUI, MASK_C_LUI, match_c_lui_with_hint, 0 },