diff mbox series

[1/3,2.42,Backport] aarch64: Remove SME2p1

Message ID bee9a590-7282-5c58-9779-ec336ea81345@e124511.cambridge.arm.com
State Not Applicable
Headers
Series [1/3,2.42,Backport] aarch64: Remove SME2p1 |

Checks

Context Check Description
snail/binutils-gdb-check fail Git am fail log

Commit Message

Andrew Carlotti Feb. 29, 2024, 5:35 p.m. UTC 
  Support for this extension is almost entirely missing in the 2.42
branch.  This patch removes the flags and documentation, to avoid
any further suggestion that this support exists.

Comments

Richard Earnshaw (lists) March 1, 2024, 5:11 p.m. UTC | #1 
On 29/02/2024 17:35, Andrew Carlotti wrote:
> Support for this extension is almost entirely missing in the 2.42
> branch.  This patch removes the flags and documentation, to avoid
> any further suggestion that this support exists.

I'm uncertain whether or not to completely remove this code.  Would it be better to just disable (comment out) the feature flag and then xfail the relevant tests?  

Adding:

#xfail *-*-*

to the affected .d files would achieve the latter.

R.

> 
> 
> diff --git a/gas/NEWS b/gas/NEWS
> index 67d806cbf89e07ea5507968086e84934649dfec6..86aa7d7334d3b58ee4e0abeba796b7214f356b30 100644
> --- a/gas/NEWS
> +++ b/gas/NEWS
> @@ -6,8 +6,6 @@ Changes in 2.42:
>  
>  * Add support for the AArch64 Scalable Vector Extension version 2.1 (SVE2.1).
>  
> -* Add support for the AArch64 Scalable Matrix Extension version 2.1 (SME2.1).
> -
>  * Add support for the AArch64 BFloat16 to BFloat16 arithmetic for SVE2 and SME2
>    (B16B16).
>  
> diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
> index 0c6de289408f4c53633e468c610623c22a0fdec8..62c428cb80ba7114440c9c65f6042259e3f99df9 100644
> --- a/gas/config/tc-aarch64.c
> +++ b/gas/config/tc-aarch64.c
> @@ -10426,7 +10426,6 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
>    {"d128",		AARCH64_FEATURE (D128),
>  			AARCH64_FEATURE (LSE128)},
>    {"b16b16",		AARCH64_FEATURE (B16B16), AARCH64_FEATURE (SVE2)},
> -  {"sme2p1",		AARCH64_FEATURE (SME2p1), AARCH64_FEATURE (SME2)},
>    {"sve2p1",		AARCH64_FEATURE (SVE2p1), AARCH64_FEATURE (SVE2)},
>    {"rcpc3",		AARCH64_FEATURE (RCPC3), AARCH64_FEATURE (RCPC2)},
>    {NULL,		AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
> diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
> index 4f97768206cd9c7efcb0cc25af497c032d66dbf8..748e7263428115c56db76b39371f9777248850a7 100644
> --- a/gas/doc/c-aarch64.texi
> +++ b/gas/doc/c-aarch64.texi
> @@ -263,8 +263,6 @@ automatically cause those extensions to be disabled.
>   @tab Enable SME I16I64 Extension.
>  @item @code{sme2} @tab @code{sme}
>   @tab Enable SME2.
> -@item @code{sme2p1} @tab @code{sme2}
> - @tab Enable SME2.1.
>  @item @code{ssbs} @tab
>   @tab Enable Speculative Store Bypassing Safe state read and write.
>  @item @code{sve} @tab @code{fcma}
> diff --git a/gas/testsuite/gas/aarch64/sme2p1-1.d b/gas/testsuite/gas/aarch64/sme2p1-1.d
> deleted file mode 100644
> index a6e7b7664024e7f03ddd1d8ece9d6c3bd1c79042..0000000000000000000000000000000000000000
> --- a/gas/testsuite/gas/aarch64/sme2p1-1.d
> +++ /dev/null
> @@ -1,42 +0,0 @@
> -#name: Test of SME2.1 movaz instructions.
> -#as: -march=armv9.4-a+sme2p1
> -#objdump: -dr
> -
> -[^:]+:     file format .*
> -
> -
> -[^:]+:
> -
> -[^:]+:
> -.*:	c006c260 	movaz	{z0.b-z1.b}, za0v.b \[w14, 6:7\]
> -.*:	c046c260 	movaz	{z0.h-z1.h}, za0v.h \[w14, 6:7\]
> -.*:	c086c220 	movaz	{z0.s-z1.s}, za0v.s \[w14, 2:3\]
> -.*:	c0c6c200 	movaz	{z0.d-z1.d}, za0v.d \[w14, 0:1\]
> -.*:	c00602e0 	movaz	{z0.b-z1.b}, za0h.b \[w12, 14:15\]
> -.*:	c0462260 	movaz	{z0.h-z1.h}, za0h.h \[w13, 6:7\]
> -.*:	c0864220 	movaz	{z0.s-z1.s}, za0h.s \[w14, 2:3\]
> -.*:	c0c66200 	movaz	{z0.d-z1.d}, za0h.d \[w15, 0:1\]
> -.*:	c006c260 	movaz	{z0.b-z1.b}, za0v.b \[w14, 6:7\]
> -.*:	c046c2e0 	movaz	{z0.h-z1.h}, za1v.h \[w14, 6:7\]
> -.*:	c086c2a0 	movaz	{z0.s-z1.s}, za2v.s \[w14, 2:3\]
> -.*:	c0c6c260 	movaz	{z0.d-z1.d}, za3v.d \[w14, 0:1\]
> -.*:	c00602e0 	movaz	{z0.b-z1.b}, za0h.b \[w12, 14:15\]
> -.*:	c04622e0 	movaz	{z0.h-z1.h}, za1h.h \[w13, 6:7\]
> -.*:	c08642a0 	movaz	{z0.s-z1.s}, za2h.s \[w14, 2:3\]
> -.*:	c0c66260 	movaz	{z0.d-z1.d}, za3h.d \[w15, 0:1\]
> -.*:	c006c660 	movaz	{z0.b-z3.b}, za0v.b \[w14, 12:15\]
> -.*:	c046c620 	movaz	{z0.h-z3.h}, za0v.h \[w14, 4:7\]
> -.*:	c086c600 	movaz	{z0.s-z3.s}, za0v.s \[w14, 0:3\]
> -.*:	c0c6c600 	movaz	{z0.d-z3.d}, za0v.d \[w14, 0:3\]
> -.*:	c0060660 	movaz	{z0.b-z3.b}, za0h.b \[w12, 12:15\]
> -.*:	c0462620 	movaz	{z0.h-z3.h}, za0h.h \[w13, 4:7\]
> -.*:	c0864600 	movaz	{z0.s-z3.s}, za0h.s \[w14, 0:3\]
> -.*:	c0c66600 	movaz	{z0.d-z3.d}, za0h.d \[w15, 0:3\]
> -.*:	c006c640 	movaz	{z0.b-z3.b}, za0v.b \[w14, 8:11\]
> -.*:	c046c660 	movaz	{z0.h-z3.h}, za1v.h \[w14, 4:7\]
> -.*:	c086c640 	movaz	{z0.s-z3.s}, za2v.s \[w14, 0:3\]
> -.*:	c0c6c660 	movaz	{z0.d-z3.d}, za3v.d \[w14, 0:3\]
> -.*:	c0060660 	movaz	{z0.b-z3.b}, za0h.b \[w12, 12:15\]
> -.*:	c0462660 	movaz	{z0.h-z3.h}, za1h.h \[w13, 4:7\]
> -.*:	c0864640 	movaz	{z0.s-z3.s}, za2h.s \[w14, 0:3\]
> -.*:	c0c66660 	movaz	{z0.d-z3.d}, za3h.d \[w15, 0:3\]
> diff --git a/gas/testsuite/gas/aarch64/sme2p1-1.s b/gas/testsuite/gas/aarch64/sme2p1-1.s
> deleted file mode 100644
> index 77481d4b874b4688e10c794e6ea9e1ff0c81ef3d..0000000000000000000000000000000000000000
> --- a/gas/testsuite/gas/aarch64/sme2p1-1.s
> +++ /dev/null
> @@ -1,39 +0,0 @@
> -	movaz {z0.b - z1.b}, ZA0V.B [w14, 6:7]
> -	movaz {z0.h - z1.h}, ZA0V.H [w14, 6:7]
> -	movaz {z0.s - z1.s}, ZA0V.S [w14, 2:3]
> -	movaz {z0.d - z1.d}, ZA0V.D [w14, 0:1]
> -
> -	movaz {z0.b - z1.b}, ZA0H.B [w12, 14:15]
> -	movaz {z0.h - z1.h}, ZA0H.H [w13, 6:7]
> -	movaz {z0.s - z1.s}, ZA0H.S [w14, 2:3]
> -	movaz {z0.d - z1.d}, ZA0H.D [w15, 0:1]
> -
> -	movaz {z0.b - z1.b}, ZA0V.B [w14, 6:7]
> -	movaz {z0.h - z1.h}, ZA1V.H [w14, 6:7]
> -	movaz {z0.s - z1.s}, ZA2V.S [w14, 2:3]
> -	movaz {z0.d - z1.d}, ZA3V.D [w14, 0:1]
> -
> -	movaz {z0.b - z1.b}, ZA0H.B [w12, 14:15]
> -	movaz {z0.h - z1.h}, ZA1H.H [w13, 6:7]
> -	movaz {z0.s - z1.s}, ZA2H.S [w14, 2:3]
> -	movaz {z0.d - z1.d}, ZA3H.D [w15, 0:1]
> -
> -	movaz {z0.b - z3.b}, ZA0V.B [w14, 12:15]
> -	movaz {z0.h - z3.h}, ZA0V.H [w14, 4:7]
> -	movaz {z0.s - z3.s}, ZA0V.S [w14, 0:3]
> -	movaz {z0.d - z3.d}, ZA0V.D [w14, 0:3]
> -
> -	movaz {z0.b - z3.b}, ZA0H.B [w12, 12:15]
> -	movaz {z0.h - z3.h}, ZA0H.H [w13, 4:7]
> -	movaz {z0.s - z3.s}, ZA0H.S [w14, 0:3]
> -	movaz {z0.d - z3.d}, ZA0H.D [w15, 0:3]
> -
> -	movaz {z0.b - z3.b}, ZA0V.B [w14, 8:11]
> -	movaz {z0.h - z3.h}, ZA1V.H [w14, 4:7]
> -	movaz {z0.s - z3.s}, ZA2V.S [w14, 0:3]
> -	movaz {z0.d - z3.d}, ZA3V.D [w14, 0:3]
> -
> -	movaz {z0.b - z3.b}, ZA0H.B [w12, 12:15]
> -	movaz {z0.h - z3.h}, ZA1H.H [w13, 4:7]
> -	movaz {z0.s - z3.s}, ZA2H.S [w14, 0:3]
> -	movaz {z0.d - z3.d}, ZA3H.D [w15, 0:3]
> diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
> index 02ee0fc2566d500359a9e89de3dfb954100f63ce..bb3151d027ccd56f83298083a2e6c744eb1f4573 100644
> --- a/include/opcode/aarch64.h
> +++ b/include/opcode/aarch64.h
> @@ -222,8 +222,6 @@ enum aarch64_feature_bit {
>    AARCH64_FEATURE_SEBEP,
>    /* SVE2.1 and SME2.1 non-widening BFloat16 instructions.  */
>    AARCH64_FEATURE_B16B16,
> -  /* SME2.1 instructions.  */
> -  AARCH64_FEATURE_SME2p1,
>    /* SVE2.1 instructions.  */
>    AARCH64_FEATURE_SVE2p1,
>    /* RCPC3 instructions.  */
> diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
> index 66d68c00725a7d7383afaecc015bf3f9dd36923a..ae4363970b0b8bc6eaa342b4199d96cacac6fd8a 100644
> --- a/opcodes/aarch64-tbl.h
> +++ b/opcodes/aarch64-tbl.h
> @@ -2643,8 +2643,6 @@ static const aarch64_feature_set aarch64_feature_d128_the =
>    AARCH64_FEATURES (2, D128, THE);
>  static const aarch64_feature_set aarch64_feature_b16b16 =
>    AARCH64_FEATURE (B16B16);
> -static const aarch64_feature_set aarch64_feature_sme2p1 =
> -  AARCH64_FEATURE (SME2p1);
>  static const aarch64_feature_set aarch64_feature_sve2p1 =
>    AARCH64_FEATURE (SVE2p1);
>  static const aarch64_feature_set aarch64_feature_rcpc3 =
> @@ -2713,7 +2711,6 @@ static const aarch64_feature_set aarch64_feature_rcpc3 =
>  #define THE	  &aarch64_feature_the
>  #define D128_THE  &aarch64_feature_d128_the
>  #define B16B16  &aarch64_feature_b16b16
> -#define SME2p1  &aarch64_feature_sme2p1
>  #define SVE2p1  &aarch64_feature_sve2p1
>  #define RCPC3	  &aarch64_feature_rcpc3
>  
> @@ -2782,9 +2779,6 @@ static const aarch64_feature_set aarch64_feature_rcpc3 =
>  #define SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
>    { NAME, OPCODE, MASK, CLASS, OP, SVE2, OPS, QUALS, \
>      FLAGS | F_STRICT, 0, TIED, NULL }
> -#define SME2p1_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
> -  { NAME, OPCODE, MASK, CLASS, OP, SME2p1, OPS, QUALS, \
> -    FLAGS | F_STRICT, 0, TIED, NULL }
>  #define SVE2_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
>    { NAME, OPCODE, MASK, CLASS, OP, SVE2, OPS, QUALS, \
>      FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL }
> @@ -6348,17 +6342,6 @@ const struct aarch64_opcode aarch64_opcode_table[] =
>    B16B16_INSN("bfmls", 0x64200c00, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_VVV_H, 0, 0),
>    B16B16_INSN("bfmul", 0x64202800, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_VVV_H, 0, 0),
>  
> -/* SME2.1 movaz instructions.  */
> -  SME2p1_INSN ("movaz", 0xc0060600, 0xffff1f83, sme2_movaz, 0, OP2 (SME_Zdnx4, SME_ZA_array_vrsb_2), OP_SVE_BB, 0, 0),
> -  SME2p1_INSN ("movaz", 0xc0460600, 0xffff1f83, sme2_movaz, 0, OP2 (SME_Zdnx4, SME_ZA_array_vrsh_2), OP_SVE_HH, 0, 0),
> -  SME2p1_INSN ("movaz", 0xc0860600, 0xffff1f83, sme2_movaz, 0, OP2 (SME_Zdnx4, SME_ZA_array_vrss_2), OP_SVE_SS, 0, 0),
> -  SME2p1_INSN ("movaz", 0xc0c60600, 0xffff1f03, sme2_movaz, 0, OP2 (SME_Zdnx4, SME_ZA_array_vrsd_2), OP_SVE_DD, 0, 0),
> -
> -  SME2p1_INSN ("movaz", 0xc0060200, 0xffff1f01, sme2_movaz, 0, OP2 (SME_Zdnx2, SME_ZA_array_vrsb_1), OP_SVE_BB, 0, 0),
> -  SME2p1_INSN ("movaz", 0xc0460200, 0xffff1f01, sme2_movaz, 0, OP2 (SME_Zdnx2, SME_ZA_array_vrsh_1), OP_SVE_HH, 0, 0),
> -  SME2p1_INSN ("movaz", 0xc0860200, 0xffff1f01, sme2_movaz, 0, OP2 (SME_Zdnx2, SME_ZA_array_vrss_1), OP_SVE_SS, 0, 0),
> -  SME2p1_INSN ("movaz", 0xc0c60200, 0xffff1f01, sme2_movaz, 0, OP2 (SME_Zdnx2, SME_ZA_array_vrsd_1), OP_SVE_DD, 0, 0),
> -
>  /* SVE2p1 Instructions.  */
>    SVE2p1_INSNC("addqv",0x04052000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
>    SVE2p1_INSNC("andqv",0x041e2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
Andrew Carlotti March 1, 2024, 5:33 p.m. UTC | #2 
On Fri, Mar 01, 2024 at 05:11:39PM +0000, Richard Earnshaw (lists) wrote:
> On 29/02/2024 17:35, Andrew Carlotti wrote:
> > Support for this extension is almost entirely missing in the 2.42
> > branch.  This patch removes the flags and documentation, to avoid
> > any further suggestion that this support exists.
> 
> I'm uncertain whether or not to completely remove this code.  Would it be better to just disable (comment out) the feature flag and then xfail the relevant tests?  
> 
> Adding:
> 
> #xfail *-*-*
> 
> to the affected .d files would achieve the latter.
> 
> R.

That's what I was originally planning to do, but then I realised that there was
little point in keeping the rest of the code present if the instructions
couldn't be used.  I'm also concerned about the possibility of incorrect
opcodes interfering with disassembly of instructions that aren't part of this
extension, although I think the only collision I'm aware of is between two
different instructions in +sve2p1.

> > 
> > 
> > diff --git a/gas/NEWS b/gas/NEWS
> > index 67d806cbf89e07ea5507968086e84934649dfec6..86aa7d7334d3b58ee4e0abeba796b7214f356b30 100644
> > --- a/gas/NEWS
> > +++ b/gas/NEWS
> > @@ -6,8 +6,6 @@ Changes in 2.42:
> >  
> >  * Add support for the AArch64 Scalable Vector Extension version 2.1 (SVE2.1).
> >  
> > -* Add support for the AArch64 Scalable Matrix Extension version 2.1 (SME2.1).
> > -
> >  * Add support for the AArch64 BFloat16 to BFloat16 arithmetic for SVE2 and SME2
> >    (B16B16).
> >  
> > diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
> > index 0c6de289408f4c53633e468c610623c22a0fdec8..62c428cb80ba7114440c9c65f6042259e3f99df9 100644
> > --- a/gas/config/tc-aarch64.c
> > +++ b/gas/config/tc-aarch64.c
> > @@ -10426,7 +10426,6 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
> >    {"d128",		AARCH64_FEATURE (D128),
> >  			AARCH64_FEATURE (LSE128)},
> >    {"b16b16",		AARCH64_FEATURE (B16B16), AARCH64_FEATURE (SVE2)},
> > -  {"sme2p1",		AARCH64_FEATURE (SME2p1), AARCH64_FEATURE (SME2)},
> >    {"sve2p1",		AARCH64_FEATURE (SVE2p1), AARCH64_FEATURE (SVE2)},
> >    {"rcpc3",		AARCH64_FEATURE (RCPC3), AARCH64_FEATURE (RCPC2)},
> >    {NULL,		AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
> > diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
> > index 4f97768206cd9c7efcb0cc25af497c032d66dbf8..748e7263428115c56db76b39371f9777248850a7 100644
> > --- a/gas/doc/c-aarch64.texi
> > +++ b/gas/doc/c-aarch64.texi
> > @@ -263,8 +263,6 @@ automatically cause those extensions to be disabled.
> >   @tab Enable SME I16I64 Extension.
> >  @item @code{sme2} @tab @code{sme}
> >   @tab Enable SME2.
> > -@item @code{sme2p1} @tab @code{sme2}
> > - @tab Enable SME2.1.
> >  @item @code{ssbs} @tab
> >   @tab Enable Speculative Store Bypassing Safe state read and write.
> >  @item @code{sve} @tab @code{fcma}
> > diff --git a/gas/testsuite/gas/aarch64/sme2p1-1.d b/gas/testsuite/gas/aarch64/sme2p1-1.d
> > deleted file mode 100644
> > index a6e7b7664024e7f03ddd1d8ece9d6c3bd1c79042..0000000000000000000000000000000000000000
> > --- a/gas/testsuite/gas/aarch64/sme2p1-1.d
> > +++ /dev/null
> > @@ -1,42 +0,0 @@
> > -#name: Test of SME2.1 movaz instructions.
> > -#as: -march=armv9.4-a+sme2p1
> > -#objdump: -dr
> > -
> > -[^:]+:     file format .*
> > -
> > -
> > -[^:]+:
> > -
> > -[^:]+:
> > -.*:	c006c260 	movaz	{z0.b-z1.b}, za0v.b \[w14, 6:7\]
> > -.*:	c046c260 	movaz	{z0.h-z1.h}, za0v.h \[w14, 6:7\]
> > -.*:	c086c220 	movaz	{z0.s-z1.s}, za0v.s \[w14, 2:3\]
> > -.*:	c0c6c200 	movaz	{z0.d-z1.d}, za0v.d \[w14, 0:1\]
> > -.*:	c00602e0 	movaz	{z0.b-z1.b}, za0h.b \[w12, 14:15\]
> > -.*:	c0462260 	movaz	{z0.h-z1.h}, za0h.h \[w13, 6:7\]
> > -.*:	c0864220 	movaz	{z0.s-z1.s}, za0h.s \[w14, 2:3\]
> > -.*:	c0c66200 	movaz	{z0.d-z1.d}, za0h.d \[w15, 0:1\]
> > -.*:	c006c260 	movaz	{z0.b-z1.b}, za0v.b \[w14, 6:7\]
> > -.*:	c046c2e0 	movaz	{z0.h-z1.h}, za1v.h \[w14, 6:7\]
> > -.*:	c086c2a0 	movaz	{z0.s-z1.s}, za2v.s \[w14, 2:3\]
> > -.*:	c0c6c260 	movaz	{z0.d-z1.d}, za3v.d \[w14, 0:1\]
> > -.*:	c00602e0 	movaz	{z0.b-z1.b}, za0h.b \[w12, 14:15\]
> > -.*:	c04622e0 	movaz	{z0.h-z1.h}, za1h.h \[w13, 6:7\]
> > -.*:	c08642a0 	movaz	{z0.s-z1.s}, za2h.s \[w14, 2:3\]
> > -.*:	c0c66260 	movaz	{z0.d-z1.d}, za3h.d \[w15, 0:1\]
> > -.*:	c006c660 	movaz	{z0.b-z3.b}, za0v.b \[w14, 12:15\]
> > -.*:	c046c620 	movaz	{z0.h-z3.h}, za0v.h \[w14, 4:7\]
> > -.*:	c086c600 	movaz	{z0.s-z3.s}, za0v.s \[w14, 0:3\]
> > -.*:	c0c6c600 	movaz	{z0.d-z3.d}, za0v.d \[w14, 0:3\]
> > -.*:	c0060660 	movaz	{z0.b-z3.b}, za0h.b \[w12, 12:15\]
> > -.*:	c0462620 	movaz	{z0.h-z3.h}, za0h.h \[w13, 4:7\]
> > -.*:	c0864600 	movaz	{z0.s-z3.s}, za0h.s \[w14, 0:3\]
> > -.*:	c0c66600 	movaz	{z0.d-z3.d}, za0h.d \[w15, 0:3\]
> > -.*:	c006c640 	movaz	{z0.b-z3.b}, za0v.b \[w14, 8:11\]
> > -.*:	c046c660 	movaz	{z0.h-z3.h}, za1v.h \[w14, 4:7\]
> > -.*:	c086c640 	movaz	{z0.s-z3.s}, za2v.s \[w14, 0:3\]
> > -.*:	c0c6c660 	movaz	{z0.d-z3.d}, za3v.d \[w14, 0:3\]
> > -.*:	c0060660 	movaz	{z0.b-z3.b}, za0h.b \[w12, 12:15\]
> > -.*:	c0462660 	movaz	{z0.h-z3.h}, za1h.h \[w13, 4:7\]
> > -.*:	c0864640 	movaz	{z0.s-z3.s}, za2h.s \[w14, 0:3\]
> > -.*:	c0c66660 	movaz	{z0.d-z3.d}, za3h.d \[w15, 0:3\]
> > diff --git a/gas/testsuite/gas/aarch64/sme2p1-1.s b/gas/testsuite/gas/aarch64/sme2p1-1.s
> > deleted file mode 100644
> > index 77481d4b874b4688e10c794e6ea9e1ff0c81ef3d..0000000000000000000000000000000000000000
> > --- a/gas/testsuite/gas/aarch64/sme2p1-1.s
> > +++ /dev/null
> > @@ -1,39 +0,0 @@
> > -	movaz {z0.b - z1.b}, ZA0V.B [w14, 6:7]
> > -	movaz {z0.h - z1.h}, ZA0V.H [w14, 6:7]
> > -	movaz {z0.s - z1.s}, ZA0V.S [w14, 2:3]
> > -	movaz {z0.d - z1.d}, ZA0V.D [w14, 0:1]
> > -
> > -	movaz {z0.b - z1.b}, ZA0H.B [w12, 14:15]
> > -	movaz {z0.h - z1.h}, ZA0H.H [w13, 6:7]
> > -	movaz {z0.s - z1.s}, ZA0H.S [w14, 2:3]
> > -	movaz {z0.d - z1.d}, ZA0H.D [w15, 0:1]
> > -
> > -	movaz {z0.b - z1.b}, ZA0V.B [w14, 6:7]
> > -	movaz {z0.h - z1.h}, ZA1V.H [w14, 6:7]
> > -	movaz {z0.s - z1.s}, ZA2V.S [w14, 2:3]
> > -	movaz {z0.d - z1.d}, ZA3V.D [w14, 0:1]
> > -
> > -	movaz {z0.b - z1.b}, ZA0H.B [w12, 14:15]
> > -	movaz {z0.h - z1.h}, ZA1H.H [w13, 6:7]
> > -	movaz {z0.s - z1.s}, ZA2H.S [w14, 2:3]
> > -	movaz {z0.d - z1.d}, ZA3H.D [w15, 0:1]
> > -
> > -	movaz {z0.b - z3.b}, ZA0V.B [w14, 12:15]
> > -	movaz {z0.h - z3.h}, ZA0V.H [w14, 4:7]
> > -	movaz {z0.s - z3.s}, ZA0V.S [w14, 0:3]
> > -	movaz {z0.d - z3.d}, ZA0V.D [w14, 0:3]
> > -
> > -	movaz {z0.b - z3.b}, ZA0H.B [w12, 12:15]
> > -	movaz {z0.h - z3.h}, ZA0H.H [w13, 4:7]
> > -	movaz {z0.s - z3.s}, ZA0H.S [w14, 0:3]
> > -	movaz {z0.d - z3.d}, ZA0H.D [w15, 0:3]
> > -
> > -	movaz {z0.b - z3.b}, ZA0V.B [w14, 8:11]
> > -	movaz {z0.h - z3.h}, ZA1V.H [w14, 4:7]
> > -	movaz {z0.s - z3.s}, ZA2V.S [w14, 0:3]
> > -	movaz {z0.d - z3.d}, ZA3V.D [w14, 0:3]
> > -
> > -	movaz {z0.b - z3.b}, ZA0H.B [w12, 12:15]
> > -	movaz {z0.h - z3.h}, ZA1H.H [w13, 4:7]
> > -	movaz {z0.s - z3.s}, ZA2H.S [w14, 0:3]
> > -	movaz {z0.d - z3.d}, ZA3H.D [w15, 0:3]
> > diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
> > index 02ee0fc2566d500359a9e89de3dfb954100f63ce..bb3151d027ccd56f83298083a2e6c744eb1f4573 100644
> > --- a/include/opcode/aarch64.h
> > +++ b/include/opcode/aarch64.h
> > @@ -222,8 +222,6 @@ enum aarch64_feature_bit {
> >    AARCH64_FEATURE_SEBEP,
> >    /* SVE2.1 and SME2.1 non-widening BFloat16 instructions.  */
> >    AARCH64_FEATURE_B16B16,
> > -  /* SME2.1 instructions.  */
> > -  AARCH64_FEATURE_SME2p1,
> >    /* SVE2.1 instructions.  */
> >    AARCH64_FEATURE_SVE2p1,
> >    /* RCPC3 instructions.  */
> > diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
> > index 66d68c00725a7d7383afaecc015bf3f9dd36923a..ae4363970b0b8bc6eaa342b4199d96cacac6fd8a 100644
> > --- a/opcodes/aarch64-tbl.h
> > +++ b/opcodes/aarch64-tbl.h
> > @@ -2643,8 +2643,6 @@ static const aarch64_feature_set aarch64_feature_d128_the =
> >    AARCH64_FEATURES (2, D128, THE);
> >  static const aarch64_feature_set aarch64_feature_b16b16 =
> >    AARCH64_FEATURE (B16B16);
> > -static const aarch64_feature_set aarch64_feature_sme2p1 =
> > -  AARCH64_FEATURE (SME2p1);
> >  static const aarch64_feature_set aarch64_feature_sve2p1 =
> >    AARCH64_FEATURE (SVE2p1);
> >  static const aarch64_feature_set aarch64_feature_rcpc3 =
> > @@ -2713,7 +2711,6 @@ static const aarch64_feature_set aarch64_feature_rcpc3 =
> >  #define THE	  &aarch64_feature_the
> >  #define D128_THE  &aarch64_feature_d128_the
> >  #define B16B16  &aarch64_feature_b16b16
> > -#define SME2p1  &aarch64_feature_sme2p1
> >  #define SVE2p1  &aarch64_feature_sve2p1
> >  #define RCPC3	  &aarch64_feature_rcpc3
> >  
> > @@ -2782,9 +2779,6 @@ static const aarch64_feature_set aarch64_feature_rcpc3 =
> >  #define SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
> >    { NAME, OPCODE, MASK, CLASS, OP, SVE2, OPS, QUALS, \
> >      FLAGS | F_STRICT, 0, TIED, NULL }
> > -#define SME2p1_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
> > -  { NAME, OPCODE, MASK, CLASS, OP, SME2p1, OPS, QUALS, \
> > -    FLAGS | F_STRICT, 0, TIED, NULL }
> >  #define SVE2_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
> >    { NAME, OPCODE, MASK, CLASS, OP, SVE2, OPS, QUALS, \
> >      FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL }
> > @@ -6348,17 +6342,6 @@ const struct aarch64_opcode aarch64_opcode_table[] =
> >    B16B16_INSN("bfmls", 0x64200c00, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_VVV_H, 0, 0),
> >    B16B16_INSN("bfmul", 0x64202800, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_VVV_H, 0, 0),
> >  
> > -/* SME2.1 movaz instructions.  */
> > -  SME2p1_INSN ("movaz", 0xc0060600, 0xffff1f83, sme2_movaz, 0, OP2 (SME_Zdnx4, SME_ZA_array_vrsb_2), OP_SVE_BB, 0, 0),
> > -  SME2p1_INSN ("movaz", 0xc0460600, 0xffff1f83, sme2_movaz, 0, OP2 (SME_Zdnx4, SME_ZA_array_vrsh_2), OP_SVE_HH, 0, 0),
> > -  SME2p1_INSN ("movaz", 0xc0860600, 0xffff1f83, sme2_movaz, 0, OP2 (SME_Zdnx4, SME_ZA_array_vrss_2), OP_SVE_SS, 0, 0),
> > -  SME2p1_INSN ("movaz", 0xc0c60600, 0xffff1f03, sme2_movaz, 0, OP2 (SME_Zdnx4, SME_ZA_array_vrsd_2), OP_SVE_DD, 0, 0),
> > -
> > -  SME2p1_INSN ("movaz", 0xc0060200, 0xffff1f01, sme2_movaz, 0, OP2 (SME_Zdnx2, SME_ZA_array_vrsb_1), OP_SVE_BB, 0, 0),
> > -  SME2p1_INSN ("movaz", 0xc0460200, 0xffff1f01, sme2_movaz, 0, OP2 (SME_Zdnx2, SME_ZA_array_vrsh_1), OP_SVE_HH, 0, 0),
> > -  SME2p1_INSN ("movaz", 0xc0860200, 0xffff1f01, sme2_movaz, 0, OP2 (SME_Zdnx2, SME_ZA_array_vrss_1), OP_SVE_SS, 0, 0),
> > -  SME2p1_INSN ("movaz", 0xc0c60200, 0xffff1f01, sme2_movaz, 0, OP2 (SME_Zdnx2, SME_ZA_array_vrsd_1), OP_SVE_DD, 0, 0),
> > -
> >  /* SVE2p1 Instructions.  */
> >    SVE2p1_INSNC("addqv",0x04052000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
> >    SVE2p1_INSNC("andqv",0x041e2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
>
diff mbox series

Patch

diff --git a/gas/NEWS b/gas/NEWS
index 67d806cbf89e07ea5507968086e84934649dfec6..86aa7d7334d3b58ee4e0abeba796b7214f356b30 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -6,8 +6,6 @@  Changes in 2.42:
 
 * Add support for the AArch64 Scalable Vector Extension version 2.1 (SVE2.1).
 
-* Add support for the AArch64 Scalable Matrix Extension version 2.1 (SME2.1).
-
 * Add support for the AArch64 BFloat16 to BFloat16 arithmetic for SVE2 and SME2
   (B16B16).
 
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 0c6de289408f4c53633e468c610623c22a0fdec8..62c428cb80ba7114440c9c65f6042259e3f99df9 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10426,7 +10426,6 @@  static const struct aarch64_option_cpu_value_table aarch64_features[] = {
   {"d128",		AARCH64_FEATURE (D128),
 			AARCH64_FEATURE (LSE128)},
   {"b16b16",		AARCH64_FEATURE (B16B16), AARCH64_FEATURE (SVE2)},
-  {"sme2p1",		AARCH64_FEATURE (SME2p1), AARCH64_FEATURE (SME2)},
   {"sve2p1",		AARCH64_FEATURE (SVE2p1), AARCH64_FEATURE (SVE2)},
   {"rcpc3",		AARCH64_FEATURE (RCPC3), AARCH64_FEATURE (RCPC2)},
   {NULL,		AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 4f97768206cd9c7efcb0cc25af497c032d66dbf8..748e7263428115c56db76b39371f9777248850a7 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -263,8 +263,6 @@  automatically cause those extensions to be disabled.
  @tab Enable SME I16I64 Extension.
 @item @code{sme2} @tab @code{sme}
  @tab Enable SME2.
-@item @code{sme2p1} @tab @code{sme2}
- @tab Enable SME2.1.
 @item @code{ssbs} @tab
  @tab Enable Speculative Store Bypassing Safe state read and write.
 @item @code{sve} @tab @code{fcma}
diff --git a/gas/testsuite/gas/aarch64/sme2p1-1.d b/gas/testsuite/gas/aarch64/sme2p1-1.d
deleted file mode 100644
index a6e7b7664024e7f03ddd1d8ece9d6c3bd1c79042..0000000000000000000000000000000000000000
--- a/gas/testsuite/gas/aarch64/sme2p1-1.d
+++ /dev/null
@@ -1,42 +0,0 @@ 
-#name: Test of SME2.1 movaz instructions.
-#as: -march=armv9.4-a+sme2p1
-#objdump: -dr
-
-[^:]+:     file format .*
-
-
-[^:]+:
-
-[^:]+:
-.*:	c006c260 	movaz	{z0.b-z1.b}, za0v.b \[w14, 6:7\]
-.*:	c046c260 	movaz	{z0.h-z1.h}, za0v.h \[w14, 6:7\]
-.*:	c086c220 	movaz	{z0.s-z1.s}, za0v.s \[w14, 2:3\]
-.*:	c0c6c200 	movaz	{z0.d-z1.d}, za0v.d \[w14, 0:1\]
-.*:	c00602e0 	movaz	{z0.b-z1.b}, za0h.b \[w12, 14:15\]
-.*:	c0462260 	movaz	{z0.h-z1.h}, za0h.h \[w13, 6:7\]
-.*:	c0864220 	movaz	{z0.s-z1.s}, za0h.s \[w14, 2:3\]
-.*:	c0c66200 	movaz	{z0.d-z1.d}, za0h.d \[w15, 0:1\]
-.*:	c006c260 	movaz	{z0.b-z1.b}, za0v.b \[w14, 6:7\]
-.*:	c046c2e0 	movaz	{z0.h-z1.h}, za1v.h \[w14, 6:7\]
-.*:	c086c2a0 	movaz	{z0.s-z1.s}, za2v.s \[w14, 2:3\]
-.*:	c0c6c260 	movaz	{z0.d-z1.d}, za3v.d \[w14, 0:1\]
-.*:	c00602e0 	movaz	{z0.b-z1.b}, za0h.b \[w12, 14:15\]
-.*:	c04622e0 	movaz	{z0.h-z1.h}, za1h.h \[w13, 6:7\]
-.*:	c08642a0 	movaz	{z0.s-z1.s}, za2h.s \[w14, 2:3\]
-.*:	c0c66260 	movaz	{z0.d-z1.d}, za3h.d \[w15, 0:1\]
-.*:	c006c660 	movaz	{z0.b-z3.b}, za0v.b \[w14, 12:15\]
-.*:	c046c620 	movaz	{z0.h-z3.h}, za0v.h \[w14, 4:7\]
-.*:	c086c600 	movaz	{z0.s-z3.s}, za0v.s \[w14, 0:3\]
-.*:	c0c6c600 	movaz	{z0.d-z3.d}, za0v.d \[w14, 0:3\]
-.*:	c0060660 	movaz	{z0.b-z3.b}, za0h.b \[w12, 12:15\]
-.*:	c0462620 	movaz	{z0.h-z3.h}, za0h.h \[w13, 4:7\]
-.*:	c0864600 	movaz	{z0.s-z3.s}, za0h.s \[w14, 0:3\]
-.*:	c0c66600 	movaz	{z0.d-z3.d}, za0h.d \[w15, 0:3\]
-.*:	c006c640 	movaz	{z0.b-z3.b}, za0v.b \[w14, 8:11\]
-.*:	c046c660 	movaz	{z0.h-z3.h}, za1v.h \[w14, 4:7\]
-.*:	c086c640 	movaz	{z0.s-z3.s}, za2v.s \[w14, 0:3\]
-.*:	c0c6c660 	movaz	{z0.d-z3.d}, za3v.d \[w14, 0:3\]
-.*:	c0060660 	movaz	{z0.b-z3.b}, za0h.b \[w12, 12:15\]
-.*:	c0462660 	movaz	{z0.h-z3.h}, za1h.h \[w13, 4:7\]
-.*:	c0864640 	movaz	{z0.s-z3.s}, za2h.s \[w14, 0:3\]
-.*:	c0c66660 	movaz	{z0.d-z3.d}, za3h.d \[w15, 0:3\]
diff --git a/gas/testsuite/gas/aarch64/sme2p1-1.s b/gas/testsuite/gas/aarch64/sme2p1-1.s
deleted file mode 100644
index 77481d4b874b4688e10c794e6ea9e1ff0c81ef3d..0000000000000000000000000000000000000000
--- a/gas/testsuite/gas/aarch64/sme2p1-1.s
+++ /dev/null
@@ -1,39 +0,0 @@ 
-	movaz {z0.b - z1.b}, ZA0V.B [w14, 6:7]
-	movaz {z0.h - z1.h}, ZA0V.H [w14, 6:7]
-	movaz {z0.s - z1.s}, ZA0V.S [w14, 2:3]
-	movaz {z0.d - z1.d}, ZA0V.D [w14, 0:1]
-
-	movaz {z0.b - z1.b}, ZA0H.B [w12, 14:15]
-	movaz {z0.h - z1.h}, ZA0H.H [w13, 6:7]
-	movaz {z0.s - z1.s}, ZA0H.S [w14, 2:3]
-	movaz {z0.d - z1.d}, ZA0H.D [w15, 0:1]
-
-	movaz {z0.b - z1.b}, ZA0V.B [w14, 6:7]
-	movaz {z0.h - z1.h}, ZA1V.H [w14, 6:7]
-	movaz {z0.s - z1.s}, ZA2V.S [w14, 2:3]
-	movaz {z0.d - z1.d}, ZA3V.D [w14, 0:1]
-
-	movaz {z0.b - z1.b}, ZA0H.B [w12, 14:15]
-	movaz {z0.h - z1.h}, ZA1H.H [w13, 6:7]
-	movaz {z0.s - z1.s}, ZA2H.S [w14, 2:3]
-	movaz {z0.d - z1.d}, ZA3H.D [w15, 0:1]
-
-	movaz {z0.b - z3.b}, ZA0V.B [w14, 12:15]
-	movaz {z0.h - z3.h}, ZA0V.H [w14, 4:7]
-	movaz {z0.s - z3.s}, ZA0V.S [w14, 0:3]
-	movaz {z0.d - z3.d}, ZA0V.D [w14, 0:3]
-
-	movaz {z0.b - z3.b}, ZA0H.B [w12, 12:15]
-	movaz {z0.h - z3.h}, ZA0H.H [w13, 4:7]
-	movaz {z0.s - z3.s}, ZA0H.S [w14, 0:3]
-	movaz {z0.d - z3.d}, ZA0H.D [w15, 0:3]
-
-	movaz {z0.b - z3.b}, ZA0V.B [w14, 8:11]
-	movaz {z0.h - z3.h}, ZA1V.H [w14, 4:7]
-	movaz {z0.s - z3.s}, ZA2V.S [w14, 0:3]
-	movaz {z0.d - z3.d}, ZA3V.D [w14, 0:3]
-
-	movaz {z0.b - z3.b}, ZA0H.B [w12, 12:15]
-	movaz {z0.h - z3.h}, ZA1H.H [w13, 4:7]
-	movaz {z0.s - z3.s}, ZA2H.S [w14, 0:3]
-	movaz {z0.d - z3.d}, ZA3H.D [w15, 0:3]
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 02ee0fc2566d500359a9e89de3dfb954100f63ce..bb3151d027ccd56f83298083a2e6c744eb1f4573 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -222,8 +222,6 @@  enum aarch64_feature_bit {
   AARCH64_FEATURE_SEBEP,
   /* SVE2.1 and SME2.1 non-widening BFloat16 instructions.  */
   AARCH64_FEATURE_B16B16,
-  /* SME2.1 instructions.  */
-  AARCH64_FEATURE_SME2p1,
   /* SVE2.1 instructions.  */
   AARCH64_FEATURE_SVE2p1,
   /* RCPC3 instructions.  */
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 66d68c00725a7d7383afaecc015bf3f9dd36923a..ae4363970b0b8bc6eaa342b4199d96cacac6fd8a 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2643,8 +2643,6 @@  static const aarch64_feature_set aarch64_feature_d128_the =
   AARCH64_FEATURES (2, D128, THE);
 static const aarch64_feature_set aarch64_feature_b16b16 =
   AARCH64_FEATURE (B16B16);
-static const aarch64_feature_set aarch64_feature_sme2p1 =
-  AARCH64_FEATURE (SME2p1);
 static const aarch64_feature_set aarch64_feature_sve2p1 =
   AARCH64_FEATURE (SVE2p1);
 static const aarch64_feature_set aarch64_feature_rcpc3 =
@@ -2713,7 +2711,6 @@  static const aarch64_feature_set aarch64_feature_rcpc3 =
 #define THE	  &aarch64_feature_the
 #define D128_THE  &aarch64_feature_d128_the
 #define B16B16  &aarch64_feature_b16b16
-#define SME2p1  &aarch64_feature_sme2p1
 #define SVE2p1  &aarch64_feature_sve2p1
 #define RCPC3	  &aarch64_feature_rcpc3
 
@@ -2782,9 +2779,6 @@  static const aarch64_feature_set aarch64_feature_rcpc3 =
 #define SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
   { NAME, OPCODE, MASK, CLASS, OP, SVE2, OPS, QUALS, \
     FLAGS | F_STRICT, 0, TIED, NULL }
-#define SME2p1_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
-  { NAME, OPCODE, MASK, CLASS, OP, SME2p1, OPS, QUALS, \
-    FLAGS | F_STRICT, 0, TIED, NULL }
 #define SVE2_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
   { NAME, OPCODE, MASK, CLASS, OP, SVE2, OPS, QUALS, \
     FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL }
@@ -6348,17 +6342,6 @@  const struct aarch64_opcode aarch64_opcode_table[] =
   B16B16_INSN("bfmls", 0x64200c00, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_VVV_H, 0, 0),
   B16B16_INSN("bfmul", 0x64202800, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_VVV_H, 0, 0),
 
-/* SME2.1 movaz instructions.  */
-  SME2p1_INSN ("movaz", 0xc0060600, 0xffff1f83, sme2_movaz, 0, OP2 (SME_Zdnx4, SME_ZA_array_vrsb_2), OP_SVE_BB, 0, 0),
-  SME2p1_INSN ("movaz", 0xc0460600, 0xffff1f83, sme2_movaz, 0, OP2 (SME_Zdnx4, SME_ZA_array_vrsh_2), OP_SVE_HH, 0, 0),
-  SME2p1_INSN ("movaz", 0xc0860600, 0xffff1f83, sme2_movaz, 0, OP2 (SME_Zdnx4, SME_ZA_array_vrss_2), OP_SVE_SS, 0, 0),
-  SME2p1_INSN ("movaz", 0xc0c60600, 0xffff1f03, sme2_movaz, 0, OP2 (SME_Zdnx4, SME_ZA_array_vrsd_2), OP_SVE_DD, 0, 0),
-
-  SME2p1_INSN ("movaz", 0xc0060200, 0xffff1f01, sme2_movaz, 0, OP2 (SME_Zdnx2, SME_ZA_array_vrsb_1), OP_SVE_BB, 0, 0),
-  SME2p1_INSN ("movaz", 0xc0460200, 0xffff1f01, sme2_movaz, 0, OP2 (SME_Zdnx2, SME_ZA_array_vrsh_1), OP_SVE_HH, 0, 0),
-  SME2p1_INSN ("movaz", 0xc0860200, 0xffff1f01, sme2_movaz, 0, OP2 (SME_Zdnx2, SME_ZA_array_vrss_1), OP_SVE_SS, 0, 0),
-  SME2p1_INSN ("movaz", 0xc0c60200, 0xffff1f01, sme2_movaz, 0, OP2 (SME_Zdnx2, SME_ZA_array_vrsd_1), OP_SVE_DD, 0, 0),
-
 /* SVE2p1 Instructions.  */
   SVE2p1_INSNC("addqv",0x04052000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
   SVE2p1_INSNC("andqv",0x041e2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),