diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 6ed657171f0f..bcf9caecff5d 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1186,6 +1186,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"smcntrpmf", "zicsr",	check_implicit_always},
   {"smstateen", "ssstateen",	check_implicit_always},
   {"smepmp", "zicsr",		check_implicit_always},
+  {"smrnmi", "zicsr",		check_implicit_always},
   {"ssaia", "zicsr",		check_implicit_always},
   {"sscofpmf", "zicsr",		check_implicit_always},
   {"ssstateen", "zicsr",	check_implicit_always},
@@ -1332,6 +1333,7 @@ static struct riscv_supported_ext riscv_supported_std_s_ext[] =
   {"smaia",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"smcntrpmf",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"smepmp",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"smrnmi",		ISA_SPEC_CLASS_DRAFT,		0, 4, 0 },
   {"smstateen",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"ssaia",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"sscofpmf",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
@@ -2545,6 +2547,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
     case INSN_CLASS_ZCB_AND_ZMMUL:
       return (riscv_subset_supports (rps, "zcb")
 	      && riscv_subset_supports (rps, "zmmul"));
+    case INSN_CLASS_SMRNMI:
+      return riscv_subset_supports (rps, "smrnmi");
     case INSN_CLASS_SVINVAL:
       return riscv_subset_supports (rps, "svinval");
     case INSN_CLASS_H:
@@ -2785,6 +2789,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return _("zcb' and `zbb");
     case INSN_CLASS_ZCB_AND_ZMMUL:
       return _("zcb' and `zmmul', or `zcb' and `m");
+    case INSN_CLASS_SMRNMI:
+      return "smrnmi";
     case INSN_CLASS_SVINVAL:
       return "svinval";
     case INSN_CLASS_H:
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index cf6e0d8b0150..538e1ee62c7f 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -76,6 +76,7 @@ enum riscv_csr_class
   CSR_CLASS_SMAIA_32,		/* Smaia, rv32 only */
   CSR_CLASS_SMCNTRPMF,		/* Smcntrpmf */
   CSR_CLASS_SMCNTRPMF_32,	/* Smcntrpmf, rv32 only */
+  CSR_CLASS_SMRNMI,		/* Smrnmi only */
   CSR_CLASS_SMSTATEEN,		/* Smstateen only */
   CSR_CLASS_SMSTATEEN_32,	/* Smstateen RV32 only */
   CSR_CLASS_SSAIA,		/* Ssaia */
@@ -1061,6 +1062,9 @@ riscv_csr_address (const char *csr_name,
       need_check_version = true;
       extension = "smcntrpmf";
       break;
+    case CSR_CLASS_SMRNMI:
+      extension = "smrnmi";
+      break;
     case CSR_CLASS_SMSTATEEN_32:
       is_rv32_only = true;
       /* Fall through.  */
diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.d b/gas/testsuite/gas/riscv/csr-dw-regnums.d
index cabb7c719181..518a6d833643 100644
--- a/gas/testsuite/gas/riscv/csr-dw-regnums.d
+++ b/gas/testsuite/gas/riscv/csr-dw-regnums.d
@@ -328,6 +328,10 @@ Contents of the .* section:
   DW_CFA_offset_extended_sf: r4898 \(minstretcfg\) at cfa\+3208
   DW_CFA_offset_extended_sf: r5921 \(mcyclecfgh\) at cfa\+7300
   DW_CFA_offset_extended_sf: r5922 \(minstretcfgh\) at cfa\+7304
+  DW_CFA_offset_extended_sf: r5952 \(mnscratch\) at cfa\+7424
+  DW_CFA_offset_extended_sf: r5953 \(mnepc\) at cfa\+7428
+  DW_CFA_offset_extended_sf: r5954 \(mncause\) at cfa\+7432
+  DW_CFA_offset_extended_sf: r5956 \(mnstatus\) at cfa\+7440
   DW_CFA_offset_extended_sf: r4876 \(mstateen0\) at cfa\+3120
   DW_CFA_offset_extended_sf: r4877 \(mstateen1\) at cfa\+3124
   DW_CFA_offset_extended_sf: r4878 \(mstateen2\) at cfa\+3128
diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.s b/gas/testsuite/gas/riscv/csr-dw-regnums.s
index 428d07707790..030d4687a506 100644
--- a/gas/testsuite/gas/riscv/csr-dw-regnums.s
+++ b/gas/testsuite/gas/riscv/csr-dw-regnums.s
@@ -326,6 +326,11 @@ _start:
 	.cfi_offset minstretcfg, 3208
 	.cfi_offset mcyclecfgh, 7300
 	.cfi_offset minstretcfgh, 7304
+	# Smrnmi extension
+	.cfi_offset mnscratch, 7424
+	.cfi_offset mnepc, 7428
+	.cfi_offset mncause, 7432
+	.cfi_offset mnstatus, 7440
 	# Smstateen extension
 	.cfi_offset mstateen0, 3120
 	.cfi_offset mstateen1, 3124
diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.d b/gas/testsuite/gas/riscv/csr-version-1p10.d
index dbdc077adac8..94836dd26b0e 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p10.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p10.d
@@ -631,6 +631,14 @@ Disassembly of section .text:
 [ 	]+[0-9a-f]+:[ 	]+72159073[ 	]+csrw[ 	]+mcyclecfgh,a1
 [ 	]+[0-9a-f]+:[ 	]+72202573[ 	]+csrr[ 	]+a0,minstretcfgh
 [ 	]+[0-9a-f]+:[ 	]+72259073[ 	]+csrw[ 	]+minstretcfgh,a1
+[ 	]+[0-9a-f]+:[ 	]+74002573[ 	]+csrr[ 	]+a0,mnscratch
+[ 	]+[0-9a-f]+:[ 	]+74059073[ 	]+csrw[ 	]+mnscratch,a1
+[ 	]+[0-9a-f]+:[ 	]+74102573[ 	]+csrr[ 	]+a0,mnepc
+[ 	]+[0-9a-f]+:[ 	]+74159073[ 	]+csrw[ 	]+mnepc,a1
+[ 	]+[0-9a-f]+:[ 	]+74202573[ 	]+csrr[ 	]+a0,mncause
+[ 	]+[0-9a-f]+:[ 	]+74259073[ 	]+csrw[ 	]+mncause,a1
+[ 	]+[0-9a-f]+:[ 	]+74402573[ 	]+csrr[ 	]+a0,mnstatus
+[ 	]+[0-9a-f]+:[ 	]+74459073[ 	]+csrw[ 	]+mnstatus,a1
 [ 	]+[0-9a-f]+:[ 	]+30c02573[ 	]+csrr[ 	]+a0,mstateen0
 [ 	]+[0-9a-f]+:[ 	]+30c59073[ 	]+csrw[ 	]+mstateen0,a1
 [ 	]+[0-9a-f]+:[ 	]+30d02573[ 	]+csrr[ 	]+a0,mstateen1
diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.l b/gas/testsuite/gas/riscv/csr-version-1p10.l
index 054179a416db..475ab3c93577 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p10.l
+++ b/gas/testsuite/gas/riscv/csr-version-1p10.l
@@ -913,6 +913,22 @@
 .*Info: macro .*
 .*Warning: invalid CSR `minstretcfgh', needs `smcntrpmf' extension
 .*Info: macro .*
+.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mncause', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mncause', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension
+.*Info: macro .*
 .*Warning: invalid CSR `mstateen0', needs `smstateen' extension
 .*Info: macro .*
 .*Warning: invalid CSR `mstateen0', needs `smstateen' extension
diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.d b/gas/testsuite/gas/riscv/csr-version-1p11.d
index 7ba88b6d1d53..12f19e80e9b7 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p11.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p11.d
@@ -631,6 +631,14 @@ Disassembly of section .text:
 [ 	]+[0-9a-f]+:[ 	]+72159073[ 	]+csrw[ 	]+mcyclecfgh,a1
 [ 	]+[0-9a-f]+:[ 	]+72202573[ 	]+csrr[ 	]+a0,minstretcfgh
 [ 	]+[0-9a-f]+:[ 	]+72259073[ 	]+csrw[ 	]+minstretcfgh,a1
+[ 	]+[0-9a-f]+:[ 	]+74002573[ 	]+csrr[ 	]+a0,mnscratch
+[ 	]+[0-9a-f]+:[ 	]+74059073[ 	]+csrw[ 	]+mnscratch,a1
+[ 	]+[0-9a-f]+:[ 	]+74102573[ 	]+csrr[ 	]+a0,mnepc
+[ 	]+[0-9a-f]+:[ 	]+74159073[ 	]+csrw[ 	]+mnepc,a1
+[ 	]+[0-9a-f]+:[ 	]+74202573[ 	]+csrr[ 	]+a0,mncause
+[ 	]+[0-9a-f]+:[ 	]+74259073[ 	]+csrw[ 	]+mncause,a1
+[ 	]+[0-9a-f]+:[ 	]+74402573[ 	]+csrr[ 	]+a0,mnstatus
+[ 	]+[0-9a-f]+:[ 	]+74459073[ 	]+csrw[ 	]+mnstatus,a1
 [ 	]+[0-9a-f]+:[ 	]+30c02573[ 	]+csrr[ 	]+a0,mstateen0
 [ 	]+[0-9a-f]+:[ 	]+30c59073[ 	]+csrw[ 	]+mstateen0,a1
 [ 	]+[0-9a-f]+:[ 	]+30d02573[ 	]+csrr[ 	]+a0,mstateen1
diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.l b/gas/testsuite/gas/riscv/csr-version-1p11.l
index cc365f1df415..43c913935b92 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p11.l
+++ b/gas/testsuite/gas/riscv/csr-version-1p11.l
@@ -909,6 +909,22 @@
 .*Info: macro .*
 .*Warning: invalid CSR `minstretcfgh', needs `smcntrpmf' extension
 .*Info: macro .*
+.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mncause', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mncause', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension
+.*Info: macro .*
 .*Warning: invalid CSR `mstateen0', needs `smstateen' extension
 .*Info: macro .*
 .*Warning: invalid CSR `mstateen0', needs `smstateen' extension
diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.d b/gas/testsuite/gas/riscv/csr-version-1p12.d
index 677820b95265..b1c1e7646ea2 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p12.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p12.d
@@ -631,6 +631,14 @@ Disassembly of section .text:
 [ 	]+[0-9a-f]+:[ 	]+72159073[ 	]+csrw[ 	]+mcyclecfgh,a1
 [ 	]+[0-9a-f]+:[ 	]+72202573[ 	]+csrr[ 	]+a0,minstretcfgh
 [ 	]+[0-9a-f]+:[ 	]+72259073[ 	]+csrw[ 	]+minstretcfgh,a1
+[ 	]+[0-9a-f]+:[ 	]+74002573[ 	]+csrr[ 	]+a0,mnscratch
+[ 	]+[0-9a-f]+:[ 	]+74059073[ 	]+csrw[ 	]+mnscratch,a1
+[ 	]+[0-9a-f]+:[ 	]+74102573[ 	]+csrr[ 	]+a0,mnepc
+[ 	]+[0-9a-f]+:[ 	]+74159073[ 	]+csrw[ 	]+mnepc,a1
+[ 	]+[0-9a-f]+:[ 	]+74202573[ 	]+csrr[ 	]+a0,mncause
+[ 	]+[0-9a-f]+:[ 	]+74259073[ 	]+csrw[ 	]+mncause,a1
+[ 	]+[0-9a-f]+:[ 	]+74402573[ 	]+csrr[ 	]+a0,mnstatus
+[ 	]+[0-9a-f]+:[ 	]+74459073[ 	]+csrw[ 	]+mnstatus,a1
 [ 	]+[0-9a-f]+:[ 	]+30c02573[ 	]+csrr[ 	]+a0,mstateen0
 [ 	]+[0-9a-f]+:[ 	]+30c59073[ 	]+csrw[ 	]+mstateen0,a1
 [ 	]+[0-9a-f]+:[ 	]+30d02573[ 	]+csrr[ 	]+a0,mstateen1
diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.l b/gas/testsuite/gas/riscv/csr-version-1p12.l
index 7a7f5f717c52..20501c5987f6 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p12.l
+++ b/gas/testsuite/gas/riscv/csr-version-1p12.l
@@ -633,6 +633,22 @@
 .*Info: macro .*
 .*Warning: invalid CSR `minstretcfgh', needs `smcntrpmf' extension
 .*Info: macro .*
+.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mncause', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mncause', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension
+.*Info: macro .*
 .*Warning: invalid CSR `mstateen0', needs `smstateen' extension
 .*Info: macro .*
 .*Warning: invalid CSR `mstateen0', needs `smstateen' extension
diff --git a/gas/testsuite/gas/riscv/csr-version-1p9p1.d b/gas/testsuite/gas/riscv/csr-version-1p9p1.d
index f4d2b04ca6a4..c40017b81638 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p9p1.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p9p1.d
@@ -631,6 +631,14 @@ Disassembly of section .text:
 [ 	]+[0-9a-f]+:[ 	]+72159073[ 	]+csrw[ 	]+0x721,a1
 [ 	]+[0-9a-f]+:[ 	]+72202573[ 	]+csrr[ 	]+a0,0x722
 [ 	]+[0-9a-f]+:[ 	]+72259073[ 	]+csrw[ 	]+0x722,a1
+[ 	]+[0-9a-f]+:[ 	]+74002573[ 	]+csrr[ 	]+a0,mnscratch
+[ 	]+[0-9a-f]+:[ 	]+74059073[ 	]+csrw[ 	]+mnscratch,a1
+[ 	]+[0-9a-f]+:[ 	]+74102573[ 	]+csrr[ 	]+a0,mnepc
+[ 	]+[0-9a-f]+:[ 	]+74159073[ 	]+csrw[ 	]+mnepc,a1
+[ 	]+[0-9a-f]+:[ 	]+74202573[ 	]+csrr[ 	]+a0,mncause
+[ 	]+[0-9a-f]+:[ 	]+74259073[ 	]+csrw[ 	]+mncause,a1
+[ 	]+[0-9a-f]+:[ 	]+74402573[ 	]+csrr[ 	]+a0,mnstatus
+[ 	]+[0-9a-f]+:[ 	]+74459073[ 	]+csrw[ 	]+mnstatus,a1
 [ 	]+[0-9a-f]+:[ 	]+30c02573[ 	]+csrr[ 	]+a0,mstateen0
 [ 	]+[0-9a-f]+:[ 	]+30c59073[ 	]+csrw[ 	]+mstateen0,a1
 [ 	]+[0-9a-f]+:[ 	]+30d02573[ 	]+csrr[ 	]+a0,mstateen1
diff --git a/gas/testsuite/gas/riscv/csr-version-1p9p1.l b/gas/testsuite/gas/riscv/csr-version-1p9p1.l
index 7fcd73ab7ddd..b375bb03ac5d 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p9p1.l
+++ b/gas/testsuite/gas/riscv/csr-version-1p9p1.l
@@ -1029,6 +1029,22 @@
 .*Info: macro .*
 .*Warning: invalid CSR `minstretcfgh' for the privileged spec `1.9.1'
 .*Info: macro .*
+.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mncause', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mncause', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension
+.*Info: macro .*
 .*Warning: invalid CSR `mstateen0', needs `smstateen' extension
 .*Info: macro .*
 .*Warning: invalid CSR `mstateen0', needs `smstateen' extension
diff --git a/gas/testsuite/gas/riscv/csr.s b/gas/testsuite/gas/riscv/csr.s
index 3d8da5488a04..e43b8a1fed1a 100644
--- a/gas/testsuite/gas/riscv/csr.s
+++ b/gas/testsuite/gas/riscv/csr.s
@@ -356,6 +356,12 @@
 	csr mcyclecfgh
 	csr minstretcfgh
 
+	# Smrnmi extension
+	csr mnscratch
+	csr mnepc
+	csr mncause
+	csr mnstatus
+
 	# Smstateen/Ssstateen extensions
 	csr mstateen0
 	csr mstateen1
diff --git a/gas/testsuite/gas/riscv/smrnmi-noarch.d b/gas/testsuite/gas/riscv/smrnmi-noarch.d
new file mode 100644
index 000000000000..d28da9736300
--- /dev/null
+++ b/gas/testsuite/gas/riscv/smrnmi-noarch.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i
+#source: smrnmi.s
+#error_output: smrnmi-noarch.l
diff --git a/gas/testsuite/gas/riscv/smrnmi-noarch.l b/gas/testsuite/gas/riscv/smrnmi-noarch.l
new file mode 100644
index 000000000000..1ad5141c1245
--- /dev/null
+++ b/gas/testsuite/gas/riscv/smrnmi-noarch.l
@@ -0,0 +1,2 @@
+.*: Assembler messages:
+.*: Error: unrecognized opcode `mnret', extension `smrnmi' required
diff --git a/gas/testsuite/gas/riscv/smrnmi.d b/gas/testsuite/gas/riscv/smrnmi.d
new file mode 100644
index 000000000000..2b628e91a103
--- /dev/null
+++ b/gas/testsuite/gas/riscv/smrnmi.d
@@ -0,0 +1,10 @@
+#as: -march=rv32i_smrnmi
+#source: smrnmi.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+70200073[ 	]+mnret
diff --git a/gas/testsuite/gas/riscv/smrnmi.s b/gas/testsuite/gas/riscv/smrnmi.s
new file mode 100644
index 000000000000..f2008bd8704e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/smrnmi.s
@@ -0,0 +1,2 @@
+target:
+	mnret
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 2a26c45f0c24..1a85762f9575 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2235,6 +2235,9 @@
 #define MASK_C_NOT 0xfc7f
 #define MATCH_C_MUL 0x9c41
 #define MASK_C_MUL 0xfc63
+/* Smrnmi instruction.  */
+#define MATCH_MNRET 0x70200073
+#define MASK_MNRET 0xffffffff
 /* Svinval instruction.  */
 #define MATCH_SINVAL_VMA 0x16000073
 #define MASK_SINVAL_VMA 0xfe007fff
@@ -2883,6 +2886,11 @@
 #define CSR_MINSTRETCFG  0x322
 #define CSR_MCYCLECFGH   0x721
 #define CSR_MINSTRETCFGH 0x722
+/* Smrnmi extension CSR addresses.  */
+#define CSR_MNSCRATCH 0x740
+#define CSR_MNEPC 0x741
+#define CSR_MNCAUSE 0x742
+#define CSR_MNSTATUS 0x744
 /* Smstateen extension */
 #define CSR_MSTATEEN0 0x30c
 #define CSR_MSTATEEN1 0x30d
@@ -3349,6 +3357,8 @@ DECLARE_INSN(hsv_b, MATCH_HSV_B, MASK_HSV_B)
 DECLARE_INSN(hsv_h, MATCH_HSV_H, MASK_HSV_H)
 DECLARE_INSN(hsv_w, MATCH_HSV_W, MASK_HSV_W)
 DECLARE_INSN(hsv_d, MATCH_HSV_D, MASK_HSV_D)
+/* Smrnmi instructions.  */
+DECLARE_INSN(mnret, MATCH_MNRET, MASK_MNRET)
 /* Zicbop instructions.  */
 DECLARE_INSN(prefetch_r, MATCH_PREFETCH_R, MASK_PREFETCH_R);
 DECLARE_INSN(prefetch_w, MATCH_PREFETCH_W, MASK_PREFETCH_W);
@@ -3874,6 +3884,11 @@ DECLARE_CSR(mcyclecfg, CSR_MCYCLECFG, CSR_CLASS_SMCNTRPMF, PRIV_SPEC_CLASS_1P10,
 DECLARE_CSR(minstretcfg, CSR_MINSTRETCFG, CSR_CLASS_SMCNTRPMF, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
 DECLARE_CSR(mcyclecfgh, CSR_MCYCLECFGH, CSR_CLASS_SMCNTRPMF_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
 DECLARE_CSR(minstretcfgh, CSR_MINSTRETCFGH, CSR_CLASS_SMCNTRPMF_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
+/* Smrnmi extension CSRs.  */
+DECLARE_CSR(mnscratch, CSR_MNSCRATCH, CSR_CLASS_SMRNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mnepc, CSR_MNEPC, CSR_CLASS_SMRNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mncause, CSR_MNCAUSE, CSR_CLASS_SMRNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mnstatus, CSR_MNSTATUS, CSR_CLASS_SMRNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 /* Smstateen/Ssstateen extensions.  */
 DECLARE_CSR(mstateen0, CSR_MSTATEEN0, CSR_CLASS_SMSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 DECLARE_CSR(mstateen1, CSR_MSTATEEN1, CSR_CLASS_SMSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 93dd5169ebce..583ee425d6ac 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -438,6 +438,7 @@ enum riscv_insn_class
   INSN_CLASS_ZCB_AND_ZBA,
   INSN_CLASS_ZCB_AND_ZBB,
   INSN_CLASS_ZCB_AND_ZMMUL,
+  INSN_CLASS_SMRNMI,
   INSN_CLASS_SVINVAL,
   INSN_CLASS_ZICBOM,
   INSN_CLASS_ZICBOP,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 8e0ae85eb064..74356a63ad28 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2011,6 +2011,9 @@ const struct riscv_opcode riscv_opcodes[] =
 {"sfence.vma", 0, INSN_CLASS_I, "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 },
 {"wfi",        0, INSN_CLASS_I, "",    MATCH_WFI, MASK_WFI, match_opcode, 0 },
 
+/* Smrnmi instructions.  */
+{"mnret",           0, INSN_CLASS_SMRNMI, "", MATCH_MNRET, MASK_MNRET, match_opcode, 0 },
+
 /* Svinval instructions.  */
 {"sinval.vma",      0, INSN_CLASS_SVINVAL, "s,t", MATCH_SINVAL_VMA, MASK_SINVAL_VMA, match_opcode, 0 },
 {"sfence.w.inval",  0, INSN_CLASS_SVINVAL, "",    MATCH_SFENCE_W_INVAL, MASK_SFENCE_W_INVAL, match_opcode, 0 },
