[v2,Binutils] aarch64: Enable Cortex-A720 CPU
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Commit Message
v2: Add missing PROFILE feature flag.
This patch adds support for the Cortex-A720 CPU to binutils.
No regressions on aarch64-none-elf.
Ok for binutils-master?
bfd/ChangeLog:
* cpu-aarch64.c: Add Cortex-A720.
gas/ChangeLog:
* NEWS: Update docs.
* config/tc-aarch64.c: Add Cortex-A720.
* doc/c-aarch64.texi: Update docs.
* testsuite/gas/aarch64/cpu-cortex-a720.d: New test.
Comments
Richard Ball <richard.ball@arm.com> writes:
> v2: Add missing PROFILE feature flag.
>
> This patch adds support for the Cortex-A720 CPU to binutils.
>
> No regressions on aarch64-none-elf.
>
> Ok for binutils-master?
>
> bfd/ChangeLog:
>
> * cpu-aarch64.c: Add Cortex-A720.
>
> gas/ChangeLog:
>
> * NEWS: Update docs.
> * config/tc-aarch64.c: Add Cortex-A720.
> * doc/c-aarch64.texi: Update docs.
> * testsuite/gas/aarch64/cpu-cortex-a720.d: New test.
OK, thanks. I was tempted to say:
>
> diff --git a/bfd/cpu-aarch64.c b/bfd/cpu-aarch64.c
> index 75a0338b90cda6ec28c1aeedb5350166c58c2db0..df0d8c8c0dd0297501cc83abc1400b5ce37509e6 100644
> --- a/bfd/cpu-aarch64.c
> +++ b/bfd/cpu-aarch64.c
> @@ -73,7 +73,8 @@ processors[] =
> { bfd_mach_aarch64, "cortex-a65" },
> { bfd_mach_aarch64, "cortex-a65ae" },
> { bfd_mach_aarch64, "cortex-a76ae" },
> - { bfd_mach_aarch64, "cortex-a77" }
> + { bfd_mach_aarch64, "cortex-a77" },
> + { bfd_mach_aarch64, "cortex-a720" }
> };
>
> static bool
> diff --git a/gas/NEWS b/gas/NEWS
> index 07ba75661052842554a478ee612b9c7a087cec1b..41eb1ab89feb8a6b375b8ff6e619701232489f00 100644
> --- a/gas/NEWS
> +++ b/gas/NEWS
> @@ -12,6 +12,8 @@
>
> * Add support for Cortex-A520 for AArch64.
>
> +* Add support for Cortex-A720 for AArch64.
> +
...that it might be better to combine these two entries, but I see
both styles are widely used.
Thanks,
Richard
> Changes in 2.41:
>
> * Add support for Intel FRED instructions.
> diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
> index e692161105a5c75fab92f707a114c20c9531f18f..19fbc7c46466ab30725e9ae16ae576aea4de5d6d 100644
> --- a/gas/config/tc-aarch64.c
> +++ b/gas/config/tc-aarch64.c
> @@ -10237,6 +10237,11 @@ static const struct aarch64_cpu_option_table aarch64_cpus[] = {
> | AARCH64_FEATURE_MEMTAG
> | AARCH64_FEATURE_SVE2_BITPERM),
> "Cortex-A710"},
> + {"cortex-a720", AARCH64_FEATURE (AARCH64_ARCH_V9_2,
> + AARCH64_FEATURE_MEMTAG
> + | AARCH64_FEATURE_PROFILE
> + | AARCH64_FEATURE_SVE2_BITPERM),
> + "Cortex-A720"},
> {"ares", AARCH64_FEATURE (AARCH64_ARCH_V8_2,
> AARCH64_FEATURE_RCPC | AARCH64_FEATURE_F16
> | AARCH64_FEATURE_DOTPROD
> diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
> index ed6b46e042290d806d98728d725b62520644e246..5e8ac0b4e7c6737e52edd6daadcd06e487572245 100644
> --- a/gas/doc/c-aarch64.texi
> +++ b/gas/doc/c-aarch64.texi
> @@ -74,6 +74,7 @@ on the target processor. The following processor names are recognized:
> @code{cortex-a510},
> @code{cortex-a520},
> @code{cortex-a710},
> +@code{cortex-a720},
> @code{ares},
> @code{exynos-m1},
> @code{falkor},
> diff --git a/gas/testsuite/gas/aarch64/cpu-cortex-a720.d b/gas/testsuite/gas/aarch64/cpu-cortex-a720.d
> new file mode 100644
> index 0000000000000000000000000000000000000000..c0b1f2b33750c4a63833f5f104bcd4dced93a9d2
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/cpu-cortex-a720.d
> @@ -0,0 +1,6 @@
> +# name: Assemble and dump for cortex-a720 CPU
> +# source: nop-asm.s
> +# as: -mcpu=cortex-a720
> +# objdump: -d -mcortex-a720
> +
> +#...
@@ -73,7 +73,8 @@ processors[] =
{ bfd_mach_aarch64, "cortex-a65" },
{ bfd_mach_aarch64, "cortex-a65ae" },
{ bfd_mach_aarch64, "cortex-a76ae" },
- { bfd_mach_aarch64, "cortex-a77" }
+ { bfd_mach_aarch64, "cortex-a77" },
+ { bfd_mach_aarch64, "cortex-a720" }
};
static bool
@@ -12,6 +12,8 @@
* Add support for Cortex-A520 for AArch64.
+* Add support for Cortex-A720 for AArch64.
+
Changes in 2.41:
* Add support for Intel FRED instructions.
@@ -10237,6 +10237,11 @@ static const struct aarch64_cpu_option_table aarch64_cpus[] = {
| AARCH64_FEATURE_MEMTAG
| AARCH64_FEATURE_SVE2_BITPERM),
"Cortex-A710"},
+ {"cortex-a720", AARCH64_FEATURE (AARCH64_ARCH_V9_2,
+ AARCH64_FEATURE_MEMTAG
+ | AARCH64_FEATURE_PROFILE
+ | AARCH64_FEATURE_SVE2_BITPERM),
+ "Cortex-A720"},
{"ares", AARCH64_FEATURE (AARCH64_ARCH_V8_2,
AARCH64_FEATURE_RCPC | AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
@@ -74,6 +74,7 @@ on the target processor. The following processor names are recognized:
@code{cortex-a510},
@code{cortex-a520},
@code{cortex-a710},
+@code{cortex-a720},
@code{ares},
@code{exynos-m1},
@code{falkor},
new file mode 100644
@@ -0,0 +1,6 @@
+# name: Assemble and dump for cortex-a720 CPU
+# source: nop-asm.s
+# as: -mcpu=cortex-a720
+# objdump: -d -mcortex-a720
+
+#...