From patchwork Sun Oct 22 03:57:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 156517 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:ce89:0:b0:403:3b70:6f57 with SMTP id p9csp587222vqx; Sat, 21 Oct 2023 20:57:31 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEHZB+PC+dkOV7XZtIldVdLoMQ0Tu1ZAG5inuuLYy7aXgA8EOuXR3wke0H/8rCq8oyuKkGm X-Received: by 2002:a05:622a:5d4:b0:41c:ad7f:5720 with SMTP id d20-20020a05622a05d400b0041cad7f5720mr6988457qtb.61.1697947051593; Sat, 21 Oct 2023 20:57:31 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1697947051; cv=pass; d=google.com; s=arc-20160816; b=XDoUzfyx9qkbq1YptTLa0Ff8C3AMW2BUnZbOPcghHo0XgJkhWgPF/BRTTyzThbU1M6 SwBwXvRrL9pq0+DVFguKYcIdArOvojab0xWLmENCZjDG7oruuN4hmi7zNPzio1FDAjDr 701Es30gnXJ1NP07xE5M8klLDiVKVY/3LlU4pAJywrU0GAKADUcmGsFE9CvI78tPQ1uB jLaLmSNfYgSDwFYoYv1610ej4PSHtYIAjivp//dwSXv++3S4NwV9PmkQVeequ8ODs8Et B1BzjmUeMjqVzcs52pww9rKFWEM5OL31a4bgLTUylS3NWQ7ZPm4q+F4cYyxf9KGet0SV mnTQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:arc-filter:dmarc-filter:delivered-to; bh=dYaCDIqRXGNf73c8GZIBZehR2Io/O/ne4jCvA/y8QSQ=; fh=lllctRxEXNnp/GZgTgmlYzny/eXMbSjNA/nbD0Q8v10=; b=pfuZgebYzUaQhVIKovOyHvXFppJKHfkbraz8plnf4fxAXuJoODc9I+aZ54HeOQHZrw BmmPTw0mzuugVymN7NDOkB/kzjI55NSNhGsh/GDVpLIh4wkgw3XOdrTvNmZpeK4MLPPP 40q2UQWVNVi8G5htHTAH6fFyZbfuPDzkiwJiyMwkMbztUdH3ee0+OWDDJ9j5vZqcTh9L Gil1wd/FJXQLp3vPvzhFA5NJ1C0cyedcJqIJhVs0aMzIJsxqm1QiE9LZHaNt5C3lKwo3 1pL3RNarI5XSuKH3BDCSay72yFUXd9SWPmWYELHQud2e0nh8WYMdshehZ717WjWzyDzU cvsA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@irq.a4lg.com header.s=2017s01 header.b=YldxzfZa; arc=pass (i=1); spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=irq.a4lg.com Received: from server2.sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id h11-20020ac85e0b000000b00419997580a3si3490910qtx.710.2023.10.21.20.57.31 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 21 Oct 2023 20:57:31 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@irq.a4lg.com header.s=2017s01 header.b=YldxzfZa; arc=pass (i=1); spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=irq.a4lg.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 50E583857353 for ; Sun, 22 Oct 2023 03:57:31 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id 37CEC3858C54 for ; Sun, 22 Oct 2023 03:57:22 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 37CEC3858C54 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=irq.a4lg.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=irq.a4lg.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 37CEC3858C54 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=153.120.152.154 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1697947046; cv=none; b=vxsW8ZwyHPqHLI+ED4Mgy3ZmHh3f7+gwb9Ky8ti13F4EhkMUoXbfpyLwo3mAw9XFgFrbagHeaqYdFl4USVxqaAN3ruV17+CFKQwkq4Gh9PSiFv4+unIovrnth9EcpuW+eGHLeP59uamQunPIpbb6pzDUzM+eqfqVPuAgNaNhOVk= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1697947046; c=relaxed/simple; bh=Vi6nC3htzDe/GhHClqKmgxSoO3+MP8oLPtQq2kpDgb0=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:Mime-Version; b=GB3Ppi1HFnnYceyY9y2ka11JTRCeEhGvn6BuHxRQT+/290X0LjX43DGyUhhQhgLCYMqeJotNz9rh3rm7Gg9EWwIYjXkNv9XdEpr1xuUzukp720l4tfL59ZUok++IV1j11N9jGMYBkG3AWnglMUIhfbmBKcPwbqZIYaYsCj7z4Kk= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 6730F300089; Sun, 22 Oct 2023 03:57:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1697947040; bh=dYaCDIqRXGNf73c8GZIBZehR2Io/O/ne4jCvA/y8QSQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Mime-Version:Content-Transfer-Encoding; b=YldxzfZa+g8H9653u49OdhPYZRdPt1cj13QK/bMSWBicborNgX3o2iOXdtMq9Bn33 9OoIJkYZ+ALrZppGmyCWQD9WUh61eAjfJqBGQJ5FKwBtoks0/FAKq+GoDl5Pw6ZNC0 7LiAuOUUIUeSIkTiK6ioKoWRxqYk9eLx2T/Rqc3c= From: Tsukasa OI To: Tsukasa OI Cc: binutils@sourceware.org Subject: [REVIEW ONLY] UNRATIFIED RISC-V: Add support for 'Zabha' subword AMO extension Date: Sun, 22 Oct 2023 03:57:15 +0000 Message-ID: In-Reply-To: <1279cd5fe3d0b809a20e18ac61f817017cca7ec9.1697946848.git.research_trasio@irq.a4lg.com> References: <1279cd5fe3d0b809a20e18ac61f817017cca7ec9.1697946848.git.research_trasio@irq.a4lg.com> Mime-Version: 1.0 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780426527571179319 X-GMAIL-MSGID: 1780426527571179319 From: Tsukasa OI [DEPENDENCY] This patch requires my 'Zacas' support patch v2 as in: [DO NOT MERGE] Despite that this extension is nearing to be Frozen, the development of this extension is not yet completed. Until this extension is frozen/ratified and final version number is determined, this patch should not be merged upstream. This commit uses unratified version 0.9 as in the latest release tag: This commit adds support for the 'Zabha' extension, adding subword (byte and half) AMO instructions. This is based on the latest commit: bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets): Make 'Zabha' to imply 'A' extension. (riscv_supported_std_z_ext): Add 'Zabha' to the supported list. (riscv_multi_subset_supports, riscv_multi_subset_supports_ext): Add handling for new instruction classes. gas/ChangeLog: * testsuite/gas/riscv/zabha.s: New test. * testsuite/gas/riscv/zabha.d: Likewise. * testsuite/gas/riscv/zabha-zacas.s: New test. * testsuite/gas/riscv/zabha-zacas.d: Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_AMOADD_B, MASK_AMOADD_B, MATCH_AMOADD_H, MASK_AMOADD_H, MATCH_AMOAND_B, MASK_AMOAND_B, MATCH_AMOAND_H, MASK_AMOAND_H, MATCH_AMOMAX_B, MASK_AMOMAX_B, MATCH_AMOMAX_H, MASK_AMOMAX_H, MATCH_AMOMAXU_B, MASK_AMOMAXU_B, MATCH_AMOMAXU_H, MASK_AMOMAXU_H, MATCH_AMOMIN_B, MASK_AMOMIN_B, MATCH_AMOMIN_H, MASK_AMOMIN_H, MATCH_AMOMINU_B, MASK_AMOMINU_B, MATCH_AMOMINU_H, MASK_AMOMINU_H, MATCH_AMOOR_B, MASK_AMOOR_B, MATCH_AMOOR_H, MASK_AMOOR_H, MATCH_AMOSWAP_B, MASK_AMOSWAP_B, MATCH_AMOSWAP_H, MASK_AMOSWAP_H, MATCH_AMOXOR_B, MASK_AMOXOR_B, MATCH_AMOXOR_H, MASK_AMOXOR_H, MATCH_AMOCAS_B, MASK_AMOCAS_B, MATCH_AMOCAS_H, MASK_AMOCAS_H): New. * opcode/riscv.h (enum riscv_insn_class): Add new instruction classes INSN_CLASS_ZABHA and INSN_CLASS_ZABHA_AND_ZACAS. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Add subword AMO instructions. --- bfd/elfxx-riscv.c | 17 ++++++ gas/testsuite/gas/riscv/zabha-zacas.d | 17 ++++++ gas/testsuite/gas/riscv/zabha-zacas.s | 9 +++ gas/testsuite/gas/riscv/zabha.d | 81 ++++++++++++++++++++++++++ gas/testsuite/gas/riscv/zabha.s | 73 ++++++++++++++++++++++++ include/opcode/riscv-opc.h | 62 ++++++++++++++++++++ include/opcode/riscv.h | 2 + opcodes/riscv-opc.c | 82 +++++++++++++++++++++++++++ 8 files changed, 343 insertions(+) create mode 100644 gas/testsuite/gas/riscv/zabha-zacas.d create mode 100644 gas/testsuite/gas/riscv/zabha-zacas.s create mode 100644 gas/testsuite/gas/riscv/zabha.d create mode 100644 gas/testsuite/gas/riscv/zabha.s base-commit: d249c8a63aec45648b2165532f79b09763870795 prerequisite-patch-id: f193a410c915c5a76a424c9401bbf1ed6fb17164 diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index b7e067794ba8..21fc99ef8c68 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1148,6 +1148,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"zhinx", "zhinxmin", check_implicit_always}, {"zhinxmin", "zfinx", check_implicit_always}, {"zfinx", "zicsr", check_implicit_always}, + {"zabha", "a", check_implicit_always}, {"zacas", "a", check_implicit_always}, {"zk", "zkn", check_implicit_always}, {"zk", "zkr", check_implicit_always}, @@ -1260,6 +1261,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zihintntl", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, {"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zabha", ISA_SPEC_CLASS_DRAFT, 0, 9, 0 }, {"zacas", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zfa", ISA_SPEC_CLASS_DRAFT, 0, 1, 0 }, @@ -2411,6 +2413,11 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "zmmul"); case INSN_CLASS_A: return riscv_subset_supports (rps, "a"); + case INSN_CLASS_ZABHA: + return riscv_subset_supports (rps, "zabha"); + case INSN_CLASS_ZABHA_AND_ZACAS: + return (riscv_subset_supports (rps, "zabha") + && riscv_subset_supports (rps, "zacas")); case INSN_CLASS_ZACAS: return riscv_subset_supports (rps, "zacas"); case INSN_CLASS_ZAWRS: @@ -2623,6 +2630,16 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return _ ("m' or `zmmul"); case INSN_CLASS_A: return "a"; + case INSN_CLASS_ZABHA: + return "zabha"; + case INSN_CLASS_ZABHA_AND_ZACAS: + if (!riscv_subset_supports (rps, "zabha") + && !riscv_subset_supports (rps, "zacas")) + return _("zabha' and `zacas"); + else if (!riscv_subset_supports (rps, "zabha")) + return "zabha"; + else + return "zacas"; case INSN_CLASS_ZACAS: return "zacas"; case INSN_CLASS_ZAWRS: diff --git a/gas/testsuite/gas/riscv/zabha-zacas.d b/gas/testsuite/gas/riscv/zabha-zacas.d new file mode 100644 index 000000000000..ea3657a6093c --- /dev/null +++ b/gas/testsuite/gas/riscv/zabha-zacas.d @@ -0,0 +1,17 @@ +#as: -march=rv32i_zabha_zacas +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+28c5852f[ ]+amocas\.b[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+2cc5852f[ ]+amocas\.b\.aq[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+2ac5852f[ ]+amocas\.b\.rl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+2ec5852f[ ]+amocas\.b\.aqrl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+28c5952f[ ]+amocas\.h[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+2cc5952f[ ]+amocas\.h\.aq[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+2ac5952f[ ]+amocas\.h\.rl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+2ec5952f[ ]+amocas\.h\.aqrl[ ]+a0,a2,\(a1\) diff --git a/gas/testsuite/gas/riscv/zabha-zacas.s b/gas/testsuite/gas/riscv/zabha-zacas.s new file mode 100644 index 000000000000..09aac3b94018 --- /dev/null +++ b/gas/testsuite/gas/riscv/zabha-zacas.s @@ -0,0 +1,9 @@ +target: + amocas.b a0, a2, (a1) + amocas.b.aq a0, a2, (a1) + amocas.b.rl a0, a2, (a1) + amocas.b.aqrl a0, a2, (a1) + amocas.h a0, a2, (a1) + amocas.h.aq a0, a2, (a1) + amocas.h.rl a0, a2, (a1) + amocas.h.aqrl a0, a2, (a1) diff --git a/gas/testsuite/gas/riscv/zabha.d b/gas/testsuite/gas/riscv/zabha.d new file mode 100644 index 000000000000..0cc39f9da821 --- /dev/null +++ b/gas/testsuite/gas/riscv/zabha.d @@ -0,0 +1,81 @@ +#as: -march=rv32i_zabha +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+08c5852f[ ]+amoswap\.b[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+0cc5852f[ ]+amoswap\.b\.aq[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+0ac5852f[ ]+amoswap\.b\.rl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+0ec5852f[ ]+amoswap\.b\.aqrl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+00c5852f[ ]+amoadd\.b[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+04c5852f[ ]+amoadd\.b\.aq[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+02c5852f[ ]+amoadd\.b\.rl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+06c5852f[ ]+amoadd\.b\.aqrl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+20c5852f[ ]+amoxor\.b[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+24c5852f[ ]+amoxor\.b\.aq[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+22c5852f[ ]+amoxor\.b\.rl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+26c5852f[ ]+amoxor\.b\.aqrl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+60c5852f[ ]+amoand\.b[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+64c5852f[ ]+amoand\.b\.aq[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+62c5852f[ ]+amoand\.b\.rl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+66c5852f[ ]+amoand\.b\.aqrl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+40c5852f[ ]+amoor\.b[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+44c5852f[ ]+amoor\.b\.aq[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+42c5852f[ ]+amoor\.b\.rl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+46c5852f[ ]+amoor\.b\.aqrl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+80c5852f[ ]+amomin\.b[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+84c5852f[ ]+amomin\.b\.aq[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+82c5852f[ ]+amomin\.b\.rl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+86c5852f[ ]+amomin\.b\.aqrl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+a0c5852f[ ]+amomax\.b[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+a4c5852f[ ]+amomax\.b\.aq[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+a2c5852f[ ]+amomax\.b\.rl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+a6c5852f[ ]+amomax\.b\.aqrl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+c0c5852f[ ]+amominu\.b[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+c4c5852f[ ]+amominu\.b\.aq[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+c2c5852f[ ]+amominu\.b\.rl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+c6c5852f[ ]+amominu\.b\.aqrl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+e0c5852f[ ]+amomaxu\.b[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+e4c5852f[ ]+amomaxu\.b\.aq[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+e2c5852f[ ]+amomaxu\.b\.rl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+e6c5852f[ ]+amomaxu\.b\.aqrl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+08c5952f[ ]+amoswap\.h[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+0cc5952f[ ]+amoswap\.h\.aq[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+0ac5952f[ ]+amoswap\.h\.rl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+0ec5952f[ ]+amoswap\.h\.aqrl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+00c5952f[ ]+amoadd\.h[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+04c5952f[ ]+amoadd\.h\.aq[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+02c5952f[ ]+amoadd\.h\.rl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+06c5952f[ ]+amoadd\.h\.aqrl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+20c5952f[ ]+amoxor\.h[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+24c5952f[ ]+amoxor\.h\.aq[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+22c5952f[ ]+amoxor\.h\.rl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+26c5952f[ ]+amoxor\.h\.aqrl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+60c5952f[ ]+amoand\.h[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+64c5952f[ ]+amoand\.h\.aq[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+62c5952f[ ]+amoand\.h\.rl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+66c5952f[ ]+amoand\.h\.aqrl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+40c5952f[ ]+amoor\.h[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+44c5952f[ ]+amoor\.h\.aq[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+42c5952f[ ]+amoor\.h\.rl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+46c5952f[ ]+amoor\.h\.aqrl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+80c5952f[ ]+amomin\.h[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+84c5952f[ ]+amomin\.h\.aq[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+82c5952f[ ]+amomin\.h\.rl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+86c5952f[ ]+amomin\.h\.aqrl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+a0c5952f[ ]+amomax\.h[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+a4c5952f[ ]+amomax\.h\.aq[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+a2c5952f[ ]+amomax\.h\.rl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+a6c5952f[ ]+amomax\.h\.aqrl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+c0c5952f[ ]+amominu\.h[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+c4c5952f[ ]+amominu\.h\.aq[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+c2c5952f[ ]+amominu\.h\.rl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+c6c5952f[ ]+amominu\.h\.aqrl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+e0c5952f[ ]+amomaxu\.h[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+e4c5952f[ ]+amomaxu\.h\.aq[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+e2c5952f[ ]+amomaxu\.h\.rl[ ]+a0,a2,\(a1\) +[ ]+[0-9a-f]+:[ ]+e6c5952f[ ]+amomaxu\.h\.aqrl[ ]+a0,a2,\(a1\) diff --git a/gas/testsuite/gas/riscv/zabha.s b/gas/testsuite/gas/riscv/zabha.s new file mode 100644 index 000000000000..ab521119a75e --- /dev/null +++ b/gas/testsuite/gas/riscv/zabha.s @@ -0,0 +1,73 @@ +target: + amoswap.b a0, a2, (a1) + amoswap.b.aq a0, a2, (a1) + amoswap.b.rl a0, a2, (a1) + amoswap.b.aqrl a0, a2, (a1) + amoadd.b a0, a2, (a1) + amoadd.b.aq a0, a2, (a1) + amoadd.b.rl a0, a2, (a1) + amoadd.b.aqrl a0, a2, (a1) + amoxor.b a0, a2, (a1) + amoxor.b.aq a0, a2, (a1) + amoxor.b.rl a0, a2, (a1) + amoxor.b.aqrl a0, a2, (a1) + amoand.b a0, a2, (a1) + amoand.b.aq a0, a2, (a1) + amoand.b.rl a0, a2, (a1) + amoand.b.aqrl a0, a2, (a1) + amoor.b a0, a2, (a1) + amoor.b.aq a0, a2, (a1) + amoor.b.rl a0, a2, (a1) + amoor.b.aqrl a0, a2, (a1) + amomin.b a0, a2, (a1) + amomin.b.aq a0, a2, (a1) + amomin.b.rl a0, a2, (a1) + amomin.b.aqrl a0, a2, (a1) + amomax.b a0, a2, (a1) + amomax.b.aq a0, a2, (a1) + amomax.b.rl a0, a2, (a1) + amomax.b.aqrl a0, a2, (a1) + amominu.b a0, a2, (a1) + amominu.b.aq a0, a2, (a1) + amominu.b.rl a0, a2, (a1) + amominu.b.aqrl a0, a2, (a1) + amomaxu.b a0, a2, (a1) + amomaxu.b.aq a0, a2, (a1) + amomaxu.b.rl a0, a2, (a1) + amomaxu.b.aqrl a0, a2, (a1) + amoswap.h a0, a2, (a1) + amoswap.h.aq a0, a2, (a1) + amoswap.h.rl a0, a2, (a1) + amoswap.h.aqrl a0, a2, (a1) + amoadd.h a0, a2, (a1) + amoadd.h.aq a0, a2, (a1) + amoadd.h.rl a0, a2, (a1) + amoadd.h.aqrl a0, a2, (a1) + amoxor.h a0, a2, (a1) + amoxor.h.aq a0, a2, (a1) + amoxor.h.rl a0, a2, (a1) + amoxor.h.aqrl a0, a2, (a1) + amoand.h a0, a2, (a1) + amoand.h.aq a0, a2, (a1) + amoand.h.rl a0, a2, (a1) + amoand.h.aqrl a0, a2, (a1) + amoor.h a0, a2, (a1) + amoor.h.aq a0, a2, (a1) + amoor.h.rl a0, a2, (a1) + amoor.h.aqrl a0, a2, (a1) + amomin.h a0, a2, (a1) + amomin.h.aq a0, a2, (a1) + amomin.h.rl a0, a2, (a1) + amomin.h.aqrl a0, a2, (a1) + amomax.h a0, a2, (a1) + amomax.h.aq a0, a2, (a1) + amomax.h.rl a0, a2, (a1) + amomax.h.aqrl a0, a2, (a1) + amominu.h a0, a2, (a1) + amominu.h.aq a0, a2, (a1) + amominu.h.rl a0, a2, (a1) + amominu.h.aqrl a0, a2, (a1) + amomaxu.h a0, a2, (a1) + amomaxu.h.aq a0, a2, (a1) + amomaxu.h.rl a0, a2, (a1) + amomaxu.h.aqrl a0, a2, (a1) diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 8fb59e3db93e..49786513a0ab 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2315,6 +2315,47 @@ #define MASK_C_NTL_S1 0xffff #define MATCH_C_NTL_ALL 0x9016 #define MASK_C_NTL_ALL 0xffff +/* Zabha instructions. */ +#define MATCH_AMOADD_B 0x2f +#define MASK_AMOADD_B 0xf800707f +#define MATCH_AMOADD_H 0x102f +#define MASK_AMOADD_H 0xf800707f +#define MATCH_AMOAND_B 0x6000002f +#define MASK_AMOAND_B 0xf800707f +#define MATCH_AMOAND_H 0x6000102f +#define MASK_AMOAND_H 0xf800707f +#define MATCH_AMOMAX_B 0xa000002f +#define MASK_AMOMAX_B 0xf800707f +#define MATCH_AMOMAX_H 0xa000102f +#define MASK_AMOMAX_H 0xf800707f +#define MATCH_AMOMAXU_B 0xe000002f +#define MASK_AMOMAXU_B 0xf800707f +#define MATCH_AMOMAXU_H 0xe000102f +#define MASK_AMOMAXU_H 0xf800707f +#define MATCH_AMOMIN_B 0x8000002f +#define MASK_AMOMIN_B 0xf800707f +#define MATCH_AMOMIN_H 0x8000102f +#define MASK_AMOMIN_H 0xf800707f +#define MATCH_AMOMINU_B 0xc000002f +#define MASK_AMOMINU_B 0xf800707f +#define MATCH_AMOMINU_H 0xc000102f +#define MASK_AMOMINU_H 0xf800707f +#define MATCH_AMOOR_B 0x4000002f +#define MASK_AMOOR_B 0xf800707f +#define MATCH_AMOOR_H 0x4000102f +#define MASK_AMOOR_H 0xf800707f +#define MATCH_AMOSWAP_B 0x800002f +#define MASK_AMOSWAP_B 0xf800707f +#define MATCH_AMOSWAP_H 0x800102f +#define MASK_AMOSWAP_H 0xf800707f +#define MATCH_AMOXOR_B 0x2000002f +#define MASK_AMOXOR_B 0xf800707f +#define MATCH_AMOXOR_H 0x2000102f +#define MASK_AMOXOR_H 0xf800707f +#define MATCH_AMOCAS_B 0x2800002f +#define MASK_AMOCAS_B 0xf800707f +#define MATCH_AMOCAS_H 0x2800102f +#define MASK_AMOCAS_H 0xf800707f /* Zacas instructions. */ #define MATCH_AMOCAS_D 0x2800302f #define MASK_AMOCAS_D 0xf800707f @@ -3377,6 +3418,27 @@ DECLARE_INSN(c_ntl_p1, MATCH_C_NTL_P1, MASK_C_NTL_P1) DECLARE_INSN(c_ntl_pall, MATCH_C_NTL_PALL, MASK_C_NTL_PALL) DECLARE_INSN(c_ntl_s1, MATCH_C_NTL_S1, MASK_C_NTL_S1) DECLARE_INSN(c_ntl_all, MATCH_C_NTL_ALL, MASK_C_NTL_ALL) +/* Zabha instructions. */ +DECLARE_INSN(amoadd_b, MATCH_AMOADD_B, MASK_AMOADD_B) +DECLARE_INSN(amoadd_h, MATCH_AMOADD_H, MASK_AMOADD_H) +DECLARE_INSN(amoand_b, MATCH_AMOAND_B, MASK_AMOAND_B) +DECLARE_INSN(amoand_h, MATCH_AMOAND_H, MASK_AMOAND_H) +DECLARE_INSN(amomax_b, MATCH_AMOMAX_B, MASK_AMOMAX_B) +DECLARE_INSN(amomax_h, MATCH_AMOMAX_H, MASK_AMOMAX_H) +DECLARE_INSN(amomaxu_b, MATCH_AMOMAXU_B, MASK_AMOMAXU_B) +DECLARE_INSN(amomaxu_h, MATCH_AMOMAXU_H, MASK_AMOMAXU_H) +DECLARE_INSN(amomin_b, MATCH_AMOMIN_B, MASK_AMOMIN_B) +DECLARE_INSN(amomin_h, MATCH_AMOMIN_H, MASK_AMOMIN_H) +DECLARE_INSN(amominu_b, MATCH_AMOMINU_B, MASK_AMOMINU_B) +DECLARE_INSN(amominu_h, MATCH_AMOMINU_H, MASK_AMOMINU_H) +DECLARE_INSN(amoor_b, MATCH_AMOOR_B, MASK_AMOOR_B) +DECLARE_INSN(amoor_h, MATCH_AMOOR_H, MASK_AMOOR_H) +DECLARE_INSN(amoswap_b, MATCH_AMOSWAP_B, MASK_AMOSWAP_B) +DECLARE_INSN(amoswap_h, MATCH_AMOSWAP_H, MASK_AMOSWAP_H) +DECLARE_INSN(amoxor_b, MATCH_AMOXOR_B, MASK_AMOXOR_B) +DECLARE_INSN(amoxor_h, MATCH_AMOXOR_H, MASK_AMOXOR_H) +DECLARE_INSN(amocas_b, MATCH_AMOCAS_B, MASK_AMOCAS_B) +DECLARE_INSN(amocas_h, MATCH_AMOCAS_H, MASK_AMOCAS_H) /* Zacas instructions. */ DECLARE_INSN(amocas_d, MATCH_AMOCAS_D, MASK_AMOCAS_D) DECLARE_INSN(amocas_q, MATCH_AMOCAS_Q, MASK_AMOCAS_Q) diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index aefbfc7db81e..f22f89bc38bd 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -396,6 +396,8 @@ enum riscv_insn_class INSN_CLASS_ZIHINTNTL_AND_C, INSN_CLASS_ZIHINTPAUSE, INSN_CLASS_ZMMUL, + INSN_CLASS_ZABHA, + INSN_CLASS_ZABHA_AND_ZACAS, INSN_CLASS_ZACAS, INSN_CLASS_ZAWRS, INSN_CLASS_F_INX, diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 58087ca19cac..5955092d6f70 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -1000,6 +1000,88 @@ const struct riscv_opcode riscv_opcodes[] = {"czero.eqz", 0, INSN_CLASS_ZICOND, "d,s,t", MATCH_CZERO_EQZ, MASK_CZERO_EQZ, match_opcode, 0 }, {"czero.nez", 0, INSN_CLASS_ZICOND, "d,s,t", MATCH_CZERO_NEZ, MASK_CZERO_NEZ, match_opcode, 0 }, +/* Zabha instructions. */ +{"amoadd.b", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOADD_B, MASK_AMOADD_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoswap.b", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOSWAP_B, MASK_AMOSWAP_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoand.b", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOAND_B, MASK_AMOAND_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoor.b", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOOR_B, MASK_AMOOR_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoxor.b", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOXOR_B, MASK_AMOXOR_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amomax.b", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAX_B, MASK_AMOMAX_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amomaxu.b", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAXU_B, MASK_AMOMAXU_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amomin.b", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMIN_B, MASK_AMOMIN_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amominu.b", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMINU_B, MASK_AMOMINU_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoadd.b.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOADD_B|MASK_AQ, MASK_AMOADD_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoswap.b.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOSWAP_B|MASK_AQ, MASK_AMOSWAP_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoand.b.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOAND_B|MASK_AQ, MASK_AMOAND_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoor.b.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOOR_B|MASK_AQ, MASK_AMOOR_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoxor.b.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOXOR_B|MASK_AQ, MASK_AMOXOR_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amomax.b.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAX_B|MASK_AQ, MASK_AMOMAX_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amomaxu.b.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAXU_B|MASK_AQ, MASK_AMOMAXU_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amomin.b.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMIN_B|MASK_AQ, MASK_AMOMIN_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amominu.b.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMINU_B|MASK_AQ, MASK_AMOMINU_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoadd.b.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOADD_B|MASK_RL, MASK_AMOADD_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoswap.b.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOSWAP_B|MASK_RL, MASK_AMOSWAP_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoand.b.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOAND_B|MASK_RL, MASK_AMOAND_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoor.b.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOOR_B|MASK_RL, MASK_AMOOR_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoxor.b.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOXOR_B|MASK_RL, MASK_AMOXOR_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amomax.b.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAX_B|MASK_RL, MASK_AMOMAX_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amomaxu.b.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAXU_B|MASK_RL, MASK_AMOMAXU_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amomin.b.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMIN_B|MASK_RL, MASK_AMOMIN_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amominu.b.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMINU_B|MASK_RL, MASK_AMOMINU_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoadd.b.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOADD_B|MASK_AQRL, MASK_AMOADD_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoswap.b.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOSWAP_B|MASK_AQRL, MASK_AMOSWAP_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoand.b.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOAND_B|MASK_AQRL, MASK_AMOAND_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoor.b.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOOR_B|MASK_AQRL, MASK_AMOOR_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoxor.b.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOXOR_B|MASK_AQRL, MASK_AMOXOR_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amomax.b.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAX_B|MASK_AQRL, MASK_AMOMAX_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amomaxu.b.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAXU_B|MASK_AQRL, MASK_AMOMAXU_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amomin.b.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMIN_B|MASK_AQRL, MASK_AMOMIN_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amominu.b.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMINU_B|MASK_AQRL, MASK_AMOMINU_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amoadd.h", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOADD_H, MASK_AMOADD_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoswap.h", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOSWAP_H, MASK_AMOSWAP_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoand.h", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOAND_H, MASK_AMOAND_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoor.h", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOOR_H, MASK_AMOOR_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoxor.h", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOXOR_H, MASK_AMOXOR_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amomax.h", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAX_H, MASK_AMOMAX_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amomaxu.h", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAXU_H, MASK_AMOMAXU_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amomin.h", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMIN_H, MASK_AMOMIN_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amominu.h", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMINU_H, MASK_AMOMINU_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoadd.h.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOADD_H|MASK_AQ, MASK_AMOADD_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoswap.h.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOSWAP_H|MASK_AQ, MASK_AMOSWAP_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoand.h.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOAND_H|MASK_AQ, MASK_AMOAND_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoor.h.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOOR_H|MASK_AQ, MASK_AMOOR_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoxor.h.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOXOR_H|MASK_AQ, MASK_AMOXOR_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amomax.h.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAX_H|MASK_AQ, MASK_AMOMAX_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amomaxu.h.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAXU_H|MASK_AQ, MASK_AMOMAXU_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amomin.h.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMIN_H|MASK_AQ, MASK_AMOMIN_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amominu.h.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMINU_H|MASK_AQ, MASK_AMOMINU_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoadd.h.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOADD_H|MASK_RL, MASK_AMOADD_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoswap.h.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOSWAP_H|MASK_RL, MASK_AMOSWAP_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoand.h.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOAND_H|MASK_RL, MASK_AMOAND_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoor.h.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOOR_H|MASK_RL, MASK_AMOOR_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoxor.h.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOXOR_H|MASK_RL, MASK_AMOXOR_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amomax.h.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAX_H|MASK_RL, MASK_AMOMAX_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amomaxu.h.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAXU_H|MASK_RL, MASK_AMOMAXU_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amomin.h.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMIN_H|MASK_RL, MASK_AMOMIN_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amominu.h.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMINU_H|MASK_RL, MASK_AMOMINU_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoadd.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOADD_H|MASK_AQRL, MASK_AMOADD_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoswap.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOSWAP_H|MASK_AQRL, MASK_AMOSWAP_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoand.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOAND_H|MASK_AQRL, MASK_AMOAND_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoor.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOOR_H|MASK_AQRL, MASK_AMOOR_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amoxor.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOXOR_H|MASK_AQRL, MASK_AMOXOR_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amomax.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAX_H|MASK_AQRL, MASK_AMOMAX_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amomaxu.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAXU_H|MASK_AQRL, MASK_AMOMAXU_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amomin.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMIN_H|MASK_AQRL, MASK_AMOMIN_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amominu.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMINU_H|MASK_AQRL, MASK_AMOMINU_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amocas.b", 0, INSN_CLASS_ZABHA_AND_ZACAS, "d,t,0(s)", MATCH_AMOCAS_B, MASK_AMOCAS_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amocas.h", 0, INSN_CLASS_ZABHA_AND_ZACAS, "d,t,0(s)", MATCH_AMOCAS_H, MASK_AMOCAS_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amocas.b.aq", 0, INSN_CLASS_ZABHA_AND_ZACAS, "d,t,0(s)", MATCH_AMOCAS_B|MASK_AQ, MASK_AMOCAS_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amocas.h.aq", 0, INSN_CLASS_ZABHA_AND_ZACAS, "d,t,0(s)", MATCH_AMOCAS_H|MASK_AQ, MASK_AMOCAS_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amocas.b.rl", 0, INSN_CLASS_ZABHA_AND_ZACAS, "d,t,0(s)", MATCH_AMOCAS_B|MASK_RL, MASK_AMOCAS_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amocas.h.rl", 0, INSN_CLASS_ZABHA_AND_ZACAS, "d,t,0(s)", MATCH_AMOCAS_H|MASK_RL, MASK_AMOCAS_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"amocas.b.aqrl", 0, INSN_CLASS_ZABHA_AND_ZACAS, "d,t,0(s)", MATCH_AMOCAS_B|MASK_AQRL, MASK_AMOCAS_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"amocas.h.aqrl", 0, INSN_CLASS_ZABHA_AND_ZACAS, "d,t,0(s)", MATCH_AMOCAS_H|MASK_AQRL, MASK_AMOCAS_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, + /* Zacas instructions. */ {"amocas.w", 0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_W, MASK_AMOCAS_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, {"amocas.w.aq", 0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_W|MASK_AQ, MASK_AMOCAS_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },