@@ -1942,16 +1942,9 @@ load_const (int reg, expressionS *ep)
static void
riscv_ext (int destreg, int srcreg, unsigned shift, bool sign)
{
- if (sign)
- {
- md_assemblef ("slli x%d, x%d, 0x%x", destreg, srcreg, shift);
- md_assemblef ("srai x%d, x%d, 0x%x", destreg, destreg, shift);
- }
- else
- {
- md_assemblef ("slli x%d, x%d, 0x%x", destreg, srcreg, shift);
- md_assemblef ("srli x%d, x%d, 0x%x", destreg, destreg, shift);
- }
+ md_assemblef ("slli x%d, x%d, %#x", destreg, srcreg, shift);
+ md_assemblef ("sr%ci x%d, x%d, %#x",
+ sign ? 'a' : 'l', destreg, destreg, shift);
}
/* Expand RISC-V Vector macros into one or more instructions. */
@@ -2075,8 +2068,8 @@ macro (struct riscv_cl_insn *ip, express
riscv_call (rd, rs1, imm_expr, *imm_reloc);
break;
- case M_ZEXTH:
- riscv_ext (rd, rs1, xlen - 16, false);
+ case M_EXTH:
+ riscv_ext (rd, rs1, xlen - 16, *ip->insn_mo->name == 's');
break;
case M_ZEXTW:
@@ -2087,10 +2080,6 @@ macro (struct riscv_cl_insn *ip, express
riscv_ext (rd, rs1, xlen - 8, true);
break;
- case M_SEXTH:
- riscv_ext (rd, rs1, xlen - 16, true);
- break;
-
case M_VMSGE:
vector_macro (ip);
break;
@@ -544,10 +544,9 @@ enum
M_CALL,
M_J,
M_LI,
- M_ZEXTH,
+ M_EXTH,
M_ZEXTW,
M_SEXTB,
- M_SEXTH,
M_VMSGE,
M_NUM_MACROS
};
@@ -1042,11 +1042,11 @@ const struct riscv_opcode riscv_opcodes[
{"sext.b", 0, INSN_CLASS_I, "d,s", 0, (int) M_SEXTB, NULL, INSN_MACRO },
{"sext.h", 0, INSN_CLASS_ZCB_AND_ZBB, "Cs,Cw", MATCH_C_SEXT_H, MASK_C_SEXT_H, match_opcode, INSN_ALIAS },
{"sext.h", 0, INSN_CLASS_ZBB, "d,s", MATCH_SEXT_H, MASK_SEXT_H, match_opcode, 0 },
-{"sext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_SEXTH, NULL, INSN_MACRO },
+{"sext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_EXTH, NULL, INSN_MACRO },
{"zext.h", 0, INSN_CLASS_ZCB_AND_ZBB, "Cs,Cw", MATCH_C_ZEXT_H, MASK_C_ZEXT_H, match_opcode, INSN_ALIAS },
{"zext.h", 32, INSN_CLASS_ZBB, "d,s", MATCH_PACK, MASK_PACK | MASK_RS2, match_opcode, 0 },
{"zext.h", 64, INSN_CLASS_ZBB, "d,s", MATCH_PACKW, MASK_PACKW | MASK_RS2, match_opcode, 0 },
-{"zext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_ZEXTH, NULL, INSN_MACRO },
+{"zext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_EXTH, NULL, INSN_MACRO },
{"orc.b", 0, INSN_CLASS_ZBB, "d,s", MATCH_GORCI | MATCH_SHAMT_ORC_B, MASK_GORCI | MASK_SHAMT, match_opcode, 0 },
{"clzw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CLZW, MASK_CLZW, match_opcode, 0 },
{"ctzw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CTZW, MASK_CTZW, match_opcode, 0 },