diff mbox series

[1/4] x86-64: LAR and LSL don't need REX.W

Message ID b0c44651-1f3f-46c6-09ff-c12bf6026bdc@suse.com
State Accepted
Headers
Series x86: misc CPU type related assembler adjustments |

Checks

Context Check Description
snail/binutils-gdb-check success Github commit url

Commit Message

Jan Beulich Feb. 10, 2023, 8:48 a.m. UTC 
  Just like we suppress emitting REX.W for e.g. MOV from/to segment
register, there's also no need for it for LAR and LSL - these can only
ever return 32-bit values and hence always zero-extend their results
anyway.

While there also drop the redundant Word from the first operand of
the second template each - this is already implied by Reg16.
diff mbox series

Patch

--- a/gas/testsuite/gas/i386/x86_64-intel.d
+++ b/gas/testsuite/gas/i386/x86_64-intel.d
@@ -260,34 +260,34 @@  Disassembly of section .text:
 [ 	]*[a-f0-9]+:	48 89 0c 25 00 00 00 00 	mov    QWORD PTR (ds:)?0x0,rcx
 [ 	]*[a-f0-9]+:	66 0f 02 d2          	lar    dx,dx
 [ 	]*[a-f0-9]+:	0f 02 d2             	lar    edx,edx
-[ 	]*[a-f0-9]+:	48 0f 02 d2          	lar    rdx,rdx
 [ 	]*[a-f0-9]+:	0f 02 d2             	lar    edx,edx
-[ 	]*[a-f0-9]+:	48 0f 02 d2          	lar    rdx,rdx
+[ 	]*[a-f0-9]+:	0f 02 d2             	lar    edx,edx
+[ 	]*[a-f0-9]+:	0f 02 d2             	lar    edx,edx
 [ 	]*[a-f0-9]+:	66 0f 02 12          	lar    dx,WORD PTR \[rdx\]
 [ 	]*[a-f0-9]+:	0f 02 12             	lar    edx,WORD PTR \[rdx\]
-[ 	]*[a-f0-9]+:	48 0f 02 12          	lar    rdx,WORD PTR \[rdx\]
+[ 	]*[a-f0-9]+:	0f 02 12             	lar    edx,WORD PTR \[rdx\]
 [ 	]*[a-f0-9]+:	66 0f 03 d2          	lsl    dx,dx
 [ 	]*[a-f0-9]+:	0f 03 d2             	lsl    edx,edx
-[ 	]*[a-f0-9]+:	48 0f 03 d2          	lsl    rdx,rdx
 [ 	]*[a-f0-9]+:	0f 03 d2             	lsl    edx,edx
-[ 	]*[a-f0-9]+:	48 0f 03 d2          	lsl    rdx,rdx
+[ 	]*[a-f0-9]+:	0f 03 d2             	lsl    edx,edx
+[ 	]*[a-f0-9]+:	0f 03 d2             	lsl    edx,edx
 [ 	]*[a-f0-9]+:	66 0f 03 12          	lsl    dx,WORD PTR \[rdx\]
 [ 	]*[a-f0-9]+:	0f 03 12             	lsl    edx,WORD PTR \[rdx\]
-[ 	]*[a-f0-9]+:	48 0f 03 12          	lsl    rdx,WORD PTR \[rdx\]
+[ 	]*[a-f0-9]+:	0f 03 12             	lsl    edx,WORD PTR \[rdx\]
 [ 	]*[a-f0-9]+:	66 0f 02 d2          	lar    dx,dx
 [ 	]*[a-f0-9]+:	0f 02 d2             	lar    edx,edx
-[ 	]*[a-f0-9]+:	48 0f 02 d2          	lar    rdx,rdx
 [ 	]*[a-f0-9]+:	0f 02 d2             	lar    edx,edx
-[ 	]*[a-f0-9]+:	48 0f 02 d2          	lar    rdx,rdx
+[ 	]*[a-f0-9]+:	0f 02 d2             	lar    edx,edx
+[ 	]*[a-f0-9]+:	0f 02 d2             	lar    edx,edx
 [ 	]*[a-f0-9]+:	66 0f 02 12          	lar    dx,WORD PTR \[rdx\]
 [ 	]*[a-f0-9]+:	0f 02 12             	lar    edx,WORD PTR \[rdx\]
-[ 	]*[a-f0-9]+:	48 0f 02 12          	lar    rdx,WORD PTR \[rdx\]
+[ 	]*[a-f0-9]+:	0f 02 12             	lar    edx,WORD PTR \[rdx\]
 [ 	]*[a-f0-9]+:	66 0f 03 d2          	lsl    dx,dx
 [ 	]*[a-f0-9]+:	0f 03 d2             	lsl    edx,edx
-[ 	]*[a-f0-9]+:	48 0f 03 d2          	lsl    rdx,rdx
 [ 	]*[a-f0-9]+:	0f 03 d2             	lsl    edx,edx
-[ 	]*[a-f0-9]+:	48 0f 03 d2          	lsl    rdx,rdx
+[ 	]*[a-f0-9]+:	0f 03 d2             	lsl    edx,edx
+[ 	]*[a-f0-9]+:	0f 03 d2             	lsl    edx,edx
 [ 	]*[a-f0-9]+:	66 0f 03 12          	lsl    dx,WORD PTR \[rdx\]
 [ 	]*[a-f0-9]+:	0f 03 12             	lsl    edx,WORD PTR \[rdx\]
-[ 	]*[a-f0-9]+:	48 0f 03 12          	lsl    rdx,WORD PTR \[rdx\]
+[ 	]*[a-f0-9]+:	0f 03 12             	lsl    edx,WORD PTR \[rdx\]
 #pass
--- a/gas/testsuite/gas/i386/x86_64.d
+++ b/gas/testsuite/gas/i386/x86_64.d
@@ -260,34 +260,34 @@  Disassembly of section .text:
 [ 	]*[a-f0-9]+:	48 89 0c 25 00 00 00 00 	mov    %rcx,0x0
 [ 	]*[a-f0-9]+:	66 0f 02 d2          	lar    %dx,%dx
 [ 	]*[a-f0-9]+:	0f 02 d2             	lar    %edx,%edx
-[ 	]*[a-f0-9]+:	48 0f 02 d2          	lar    %rdx,%rdx
 [ 	]*[a-f0-9]+:	0f 02 d2             	lar    %edx,%edx
-[ 	]*[a-f0-9]+:	48 0f 02 d2          	lar    %rdx,%rdx
+[ 	]*[a-f0-9]+:	0f 02 d2             	lar    %edx,%edx
+[ 	]*[a-f0-9]+:	0f 02 d2             	lar    %edx,%edx
 [ 	]*[a-f0-9]+:	66 0f 02 12          	lar    \(%rdx\),%dx
 [ 	]*[a-f0-9]+:	0f 02 12             	lar    \(%rdx\),%edx
-[ 	]*[a-f0-9]+:	48 0f 02 12          	lar    \(%rdx\),%rdx
+[ 	]*[a-f0-9]+:	0f 02 12             	lar    \(%rdx\),%edx
 [ 	]*[a-f0-9]+:	66 0f 03 d2          	lsl    %dx,%dx
 [ 	]*[a-f0-9]+:	0f 03 d2             	lsl    %edx,%edx
-[ 	]*[a-f0-9]+:	48 0f 03 d2          	lsl    %rdx,%rdx
 [ 	]*[a-f0-9]+:	0f 03 d2             	lsl    %edx,%edx
-[ 	]*[a-f0-9]+:	48 0f 03 d2          	lsl    %rdx,%rdx
+[ 	]*[a-f0-9]+:	0f 03 d2             	lsl    %edx,%edx
+[ 	]*[a-f0-9]+:	0f 03 d2             	lsl    %edx,%edx
 [ 	]*[a-f0-9]+:	66 0f 03 12          	lsl    \(%rdx\),%dx
 [ 	]*[a-f0-9]+:	0f 03 12             	lsl    \(%rdx\),%edx
-[ 	]*[a-f0-9]+:	48 0f 03 12          	lsl    \(%rdx\),%rdx
+[ 	]*[a-f0-9]+:	0f 03 12             	lsl    \(%rdx\),%edx
 [ 	]*[a-f0-9]+:	66 0f 02 d2          	lar    %dx,%dx
 [ 	]*[a-f0-9]+:	0f 02 d2             	lar    %edx,%edx
-[ 	]*[a-f0-9]+:	48 0f 02 d2          	lar    %rdx,%rdx
 [ 	]*[a-f0-9]+:	0f 02 d2             	lar    %edx,%edx
-[ 	]*[a-f0-9]+:	48 0f 02 d2          	lar    %rdx,%rdx
+[ 	]*[a-f0-9]+:	0f 02 d2             	lar    %edx,%edx
+[ 	]*[a-f0-9]+:	0f 02 d2             	lar    %edx,%edx
 [ 	]*[a-f0-9]+:	66 0f 02 12          	lar    \(%rdx\),%dx
 [ 	]*[a-f0-9]+:	0f 02 12             	lar    \(%rdx\),%edx
-[ 	]*[a-f0-9]+:	48 0f 02 12          	lar    \(%rdx\),%rdx
+[ 	]*[a-f0-9]+:	0f 02 12             	lar    \(%rdx\),%edx
 [ 	]*[a-f0-9]+:	66 0f 03 d2          	lsl    %dx,%dx
 [ 	]*[a-f0-9]+:	0f 03 d2             	lsl    %edx,%edx
-[ 	]*[a-f0-9]+:	48 0f 03 d2          	lsl    %rdx,%rdx
 [ 	]*[a-f0-9]+:	0f 03 d2             	lsl    %edx,%edx
-[ 	]*[a-f0-9]+:	48 0f 03 d2          	lsl    %rdx,%rdx
+[ 	]*[a-f0-9]+:	0f 03 d2             	lsl    %edx,%edx
+[ 	]*[a-f0-9]+:	0f 03 d2             	lsl    %edx,%edx
 [ 	]*[a-f0-9]+:	66 0f 03 12          	lsl    \(%rdx\),%dx
 [ 	]*[a-f0-9]+:	0f 03 12             	lsl    \(%rdx\),%edx
-[ 	]*[a-f0-9]+:	48 0f 03 12          	lsl    \(%rdx\),%rdx
+[ 	]*[a-f0-9]+:	0f 03 12             	lsl    \(%rdx\),%edx
 #pass
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -567,16 +567,16 @@  nop, 0x90, 0, NoSuf|RepPrefixOk, {}
 
 // Protection control.
 arpl, 0x63, i286|No64, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16, Reg16|Word|Unspecified|BaseIndex }
-lar, 0xf02, i286, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 }
-lar, 0xf02, i286, Modrm|No_bSuf|No_sSuf, { Reg16|Word|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+lar, 0xf02, i286, Modrm|CheckOperandSize|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 }
+lar, 0xf02, i286, Modrm|No_bSuf|No_sSuf|NoRex64, { Reg16|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
 lgdt, 0xf01/2, i286|No64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex }
 lgdt, 0xf01/2, x64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex }
 lidt, 0xf01/3, i286|No64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex }
 lidt, 0xf01/3, x64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex }
 lldt, 0xf00/2, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex }
 lmsw, 0xf01/6, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex }
-lsl, 0xf03, i286, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 }
-lsl, 0xf03, i286, Modrm|No_bSuf|No_sSuf, { Reg16|Word|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+lsl, 0xf03, i286, Modrm|CheckOperandSize|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 }
+lsl, 0xf03, i286, Modrm|No_bSuf|No_sSuf|NoRex64, { Reg16|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
 ltr, 0xf00/3, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex }
 
 sgdt, 0xf01/0, i286|No64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex }