diff mbox series

[2/2] x86: use swap_2_operands() in build_vex_prefix()

Message ID a68e2ee4-9198-664e-4e62-245ff29494fc@suse.com
State Unresolved
Headers
Series x86: assorted small tidies |

Checks

Context Check Description
snail/binutils-gdb-check warning Git am fail log

Commit Message

Jan Beulich Feb. 24, 2023, 1:09 p.m. UTC 
  Open-coding part of what may eventually be needed is somewhat risky.
Let's use the function we have, taking care of all pieces of data which
may need swapping, no matter that
- right now i.flags[] and i.reloc[] aren't relevant here (yet),
- EVEX masking and embedded broadcast aren't applicable.
diff mbox series

Patch

--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -3593,16 +3593,9 @@  build_vex_prefix (const insn_template *t
       && (i.tm.opcode_modifier.load || i.tm.opcode_modifier.d)
       && i.rex == REX_B)
     {
-      unsigned int xchg = i.operands - 1;
-      union i386_op temp_op;
-      i386_operand_type temp_type;
-
-      temp_type = i.types[xchg];
-      i.types[xchg] = i.types[0];
-      i.types[0] = temp_type;
-      temp_op = i.op[xchg];
-      i.op[xchg] = i.op[0];
-      i.op[0] = temp_op;
+      unsigned int xchg;
+
+      swap_2_operands (0, i.operands - 1);
 
       gas_assert (i.rm.mode == 3);
 
@@ -3632,8 +3625,6 @@  build_vex_prefix (const insn_template *t
       && !(i.vex.register_specifier->reg_flags & RegRex))
     {
       unsigned int xchg = i.operands - i.reg_operands;
-      union i386_op temp_op;
-      i386_operand_type temp_type;
 
       gas_assert (i.tm.opcode_space == SPACE_0F);
       gas_assert (!i.tm.opcode_modifier.sae);
@@ -3641,12 +3632,7 @@  build_vex_prefix (const insn_template *t
                                       &i.types[i.operands - 3]));
       gas_assert (i.rm.mode == 3);
 
-      temp_type = i.types[xchg];
-      i.types[xchg] = i.types[xchg + 1];
-      i.types[xchg + 1] = temp_type;
-      temp_op = i.op[xchg];
-      i.op[xchg] = i.op[xchg + 1];
-      i.op[xchg + 1] = temp_op;
+      swap_2_operands (xchg, xchg + 1);
 
       i.rex = 0;
       xchg = i.rm.regmem | 8;