new file mode 100644
@@ -0,0 +1,15 @@
+#as: -mfuture
+#objdump: -dr -Mfuture -Mraw
+#name: Future tests - raw disassembly
+
+.*
+
+
+Disassembly of section \.text:
+
+0+0 <_start>:
+.*: (90 58 4c 7d|7d 4c 58 90) subfus r10,0,r12,r11
+.*: (91 58 4c 7d|7d 4c 58 91) subfus\. r10,0,r12,r11
+.*: (90 ac 96 7e|7e 96 ac 90) subfus r20,1,r22,r21
+.*: (91 ac 96 7e|7e 96 ac 91) subfus\. r20,1,r22,r21
+#pass
new file mode 100644
@@ -0,0 +1,6 @@
+ .text
+_start:
+ subwus 10,11,12
+ subwus. 10,11,12
+ subdus 20,21,22
+ subdus. 20,21,22
@@ -146,8 +146,10 @@ run_dump_test "scalarquad"
run_dump_test "rop"
run_dump_test "rop-checks"
run_dump_test "rfc02653"
+run_dump_test "rfc02655"
run_dump_test "rfc02656"
run_dump_test "rfc02658"
+run_dump_test "future-raw"
run_dump_test "dcbt"
run_dump_test "pr27676"
new file mode 100644
@@ -0,0 +1,19 @@
+#as: -mfuture
+#objdump: -dr -Mfuture
+#name: RFC02655 tests
+
+.*
+
+
+Disassembly of section \.text:
+
+0+0 <_start>:
+.*: (90 58 4c 7d|7d 4c 58 90) subwus r10,r11,r12
+.*: (90 58 4c 7d|7d 4c 58 90) subwus r10,r11,r12
+.*: (91 58 4c 7d|7d 4c 58 91) subwus\. r10,r11,r12
+.*: (91 58 4c 7d|7d 4c 58 91) subwus\. r10,r11,r12
+.*: (90 ac 96 7e|7e 96 ac 90) subdus r20,r21,r22
+.*: (90 ac 96 7e|7e 96 ac 90) subdus r20,r21,r22
+.*: (91 ac 96 7e|7e 96 ac 91) subdus\. r20,r21,r22
+.*: (91 ac 96 7e|7e 96 ac 91) subdus\. r20,r21,r22
+#pass
new file mode 100644
@@ -0,0 +1,10 @@
+ .text
+_start:
+ subfus 10,0,12,11
+ subwus 10,11,12
+ subfus. 10,0,12,11
+ subwus. 10,11,12
+ subfus 20,1,22,21
+ subdus 20,21,22
+ subfus. 20,1,22,21
+ subdus. 20,21,22
@@ -3704,6 +3704,8 @@ const struct powerpc_operand powerpc_operands[] =
#define BO16 PSWM
/* The pst field in a SVRM form instruction. */
#define pst PSWM
+ /* The L field in a XO form instruction. */
+#define XOL PSWM
{ 0x1, 10, 0, 0, 0 },
/* IDX bits for quantization in the pair singles instructions. */
@@ -4775,6 +4777,7 @@ const unsigned int num_powerpc_operands = ARRAY_SIZE (powerpc_operands);
| ((((uint64_t)(oe)) & 1) << 10) \
| (((unsigned long)(rc)) & 1))
#define XO_MASK XO (0x3f, 0x1ff, 1, 1)
+#define XOL_MASK XO (0x3f, 0x1ff, 0, 1)
/* An XO_MASK with the RB field fixed. */
#define XORB_MASK (XO_MASK | RB_MASK)
@@ -7212,6 +7215,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"td", X(31,68), X_MASK, PPC64, 0, {TO, RA, RB}},
{"lwfcmx", APU(31,71,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
+{"subwus", XO(31,72,0,0), XO_MASK, FUTURE, EXT, {RT, RB, RA}},
+{"subwus.", XO(31,72,0,1), XO_MASK, FUTURE, EXT, {RT, RB, RA}},
+{"subdus", XO(31,72,1,0), XO_MASK, FUTURE, EXT, {RT, RB, RA}},
+{"subdus.", XO(31,72,1,1), XO_MASK, FUTURE, EXT, {RT, RB, RA}},
+{"subfus", XO(31,72,0,0), XOL_MASK, FUTURE, 0, {RT, XOL, RA, RB}},
+{"subfus.", XO(31,72,0,1), XOL_MASK, FUTURE, 0, {RT, XOL, RA, RB}},
{"mulhd", XO(31,73,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
{"mulhd.", XO(31,73,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},