diff mbox series

PowerPC SPE disassembly and tests

Message ID Y0lJxxYoeD5iDYAD@squeak.grove.modra.org
State Unresolved
Headers
Series PowerPC SPE disassembly and tests |

Checks

Context Check Description
snail/binutils-gdb-check warning Git am fail log

Commit Message

Alan Modra Oct. 14, 2022, 11:36 a.m. UTC 
  Where sub and subf forms of an instruction exist we generally
disassemble to the extended insn sub form rather than the underlying
machine subf instruction.  Do so for SPE evsubw and evsubiw too.

spe_ambiguous.d always was a bit too optimistic.  There is no sensible
way to disassemble identical bytes back to different and original
source.  Instead change the test to check -Mraw results.

gas/
	* testsuite/gas/ppc/ppc.exp: Run spe_ambiguous test.
	* testsuite/gas/ppc/spe.d: Expect evsubw and evsubiw rather than
	evsubfw and evsubifw.
	* testsuite/gas/ppc/spe_ambiguous.s: Test evnor form equivalent
	to evnot.
	* testsuite/gas/ppc/spe_ambiguous.d: Test Mraw.
opcodes/
	* ppc-opc.c (powerpc_opcodes): Move evsubw before evsubfw and
	evsubiw before evsubifw and mark EXT.
diff mbox series

Patch

diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index 9a18ce2e2ff..1bfd375ccd6 100644
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -94,10 +94,7 @@  run_dump_test "efs2"
 run_dump_test "spe2"
 run_dump_test "spe2-checks"
 run_dump_test "spe"
-
-setup_xfail "*-*-*"
 run_dump_test "spe_ambiguous"
-
 run_dump_test "altivec"
 run_dump_test "altivec2"
 run_dump_test "altivec3"
diff --git a/gas/testsuite/gas/ppc/spe.d b/gas/testsuite/gas/ppc/spe.d
index 958bdf1e57b..7429879329b 100644
--- a/gas/testsuite/gas/ppc/spe.d
+++ b/gas/testsuite/gas/ppc/spe.d
@@ -10,10 +10,10 @@  Disassembly of section .text:
 00000000 <.text>:
 .*:	10 01 12 00 	evaddw  r0,r1,r2
 .*:	10 1f 12 02 	evaddiw r0,r2,31
-.*:	10 01 12 04 	evsubfw r0,r1,r2
-.*:	10 01 12 04 	evsubfw r0,r1,r2
-.*:	10 1f 12 06 	evsubifw r0,31,r2
-.*:	10 1f 12 06 	evsubifw r0,31,r2
+.*:	10 01 12 04 	evsubw  r0,r2,r1
+.*:	10 01 12 04 	evsubw  r0,r2,r1
+.*:	10 1f 12 06 	evsubiw r0,r2,31
+.*:	10 1f 12 06 	evsubiw r0,r2,31
 .*:	10 01 02 08 	evabs   r0,r1
 .*:	10 01 02 09 	evneg   r0,r1
 .*:	10 01 02 0a 	evextsb r0,r1
diff --git a/gas/testsuite/gas/ppc/spe_ambiguous.d b/gas/testsuite/gas/ppc/spe_ambiguous.d
index 2e0b1d3594f..3cbbb1a1610 100644
--- a/gas/testsuite/gas/ppc/spe_ambiguous.d
+++ b/gas/testsuite/gas/ppc/spe_ambiguous.d
@@ -1,6 +1,6 @@ 
 #as: -a32 -mbig -mvle
-#objdump: -d -Mspe
-#name: Validate SPE instructions
+#objdump: -d -Mspe -Mraw
+#name: Validate SPE raw instructions
 
 .*: +file format elf.*-powerpc.*
 
@@ -8,8 +8,8 @@  Disassembly of section .text:
 
 00000000 <.text>:
    0:	10 01 12 04 	evsubfw r0,r1,r2
-   4:	10 01 12 04 	evsubw r0,r2,r1
+   4:	10 01 12 04 	evsubfw r0,r1,r2
    8:	10 1f 12 06 	evsubifw r0,31,r2
-   c:	10 1f 12 06 	evsubiw r0,r2,31
-  10:	10 01 12 18 	evnor   r0,r1,r2
-  14:	10 01 0a 18 	evnot   r0,r1
+   c:	10 1f 12 06 	evsubifw r0,31,r2
+  10:	10 01 0a 18 	evnor   r0,r1,r1
+  14:	10 01 0a 18 	evnor   r0,r1,r1
diff --git a/gas/testsuite/gas/ppc/spe_ambiguous.s b/gas/testsuite/gas/ppc/spe_ambiguous.s
index b60e02bfb7f..97de2eb3a96 100644
--- a/gas/testsuite/gas/ppc/spe_ambiguous.s
+++ b/gas/testsuite/gas/ppc/spe_ambiguous.s
@@ -17,5 +17,5 @@ 
 	evsubw          rS, rB, rA
 	evsubifw        rS, UIMM, rB
 	evsubiw         rS, rB, UIMM
-	evnor           rS, rA, rB
+	evnor           rS, rA, rA
 	evnot           rS, rA
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 1d274c39147..e1b67647da6 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -5201,12 +5201,12 @@  const struct powerpc_opcode powerpc_opcodes[] = {
 {"vmul10uq",	VX (4, 513),	VXVB_MASK,   PPCVEC3,	0,		{VD, VA}},
 {"evaddiw",	VX (4, 514),	VX_MASK,     PPCSPE,	0,		{RS, RB, UIMM}},
 {"vminub",	VX (4, 514),	VX_MASK,     PPCVEC,	0,		{VD, VA, VB}},
+{"evsubw",	VX (4, 516),	VX_MASK,     PPCSPE,	EXT,		{RS, RB, RA}},
 {"evsubfw",	VX (4, 516),	VX_MASK,     PPCSPE,	0,		{RS, RA, RB}},
-{"evsubw",	VX (4, 516),	VX_MASK,     PPCSPE,	0,		{RS, RB, RA}},
 {"vsrb",	VX (4, 516),	VX_MASK,     PPCVEC,	0,		{VD, VA, VB}},
 {"vsrq",	VX (4, 517),	VX_MASK,     POWER10,	0,		{VD, VA, VB}},
+{"evsubiw",	VX (4, 518),	VX_MASK,     PPCSPE,	EXT,		{RS, RB, UIMM}},
 {"evsubifw",	VX (4, 518),	VX_MASK,     PPCSPE,	0,		{RS, UIMM, RB}},
-{"evsubiw",	VX (4, 518),	VX_MASK,     PPCSPE,	0,		{RS, RB, UIMM}},
 {"vcmpgtub",	VXR(4, 518,0),	VXR_MASK,    PPCVEC,	0,		{VD, VA, VB}},
 {"evabs",	VX (4, 520),	VX_MASK,     PPCSPE,	0,		{RS, RA}},
 {"vmuleub",	VX (4, 520),	VX_MASK,     PPCVEC,	0,		{VD, VA, VB}},