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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id lu16-20020a170906fad000b00a3d5efc65e0sm5486296ejb.91.2024.02.23.03.29.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 23 Feb 2024 03:29:01 -0800 (PST) Message-ID: <9f36e4cc-46c9-4a88-9b4d-a40298ea3c12@suse.com> Date: Fri, 23 Feb 2024 12:29:00 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH 3/6] Arm64: check tied operand specifier in aarch64-gen Content-Language: en-US From: Jan Beulich To: Binutils Cc: Richard Earnshaw , Marcus Shawcroft , Nick Clifton References: <2dbdd49f-2302-4dbc-98ba-0bdaf3c4cad2@suse.com> Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <2dbdd49f-2302-4dbc-98ba-0bdaf3c4cad2@suse.com> X-Spam-Status: No, score=-3025.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791688974696560070 X-GMAIL-MSGID: 1791688974696560070 Make sure that field actually matches the specified operands. Don't follow existing F_PSEUDO checking in using assertions, though. Print meaingful error messages, thus - while not having a line number available - at least providing some indication of where things are wrong. Fix SVE2.1's extq accordingly, but don't extend the testsuite there: There are further issues with its operands (SVE_Zm_imm4 doesn't look to be correct to use there, as that describes an indexed vector register, while here a separate vector register and immediate operand are to be specified). --- a/opcodes/aarch64-gen.c +++ b/opcodes/aarch64-gen.c @@ -129,6 +129,7 @@ read_table (const struct aarch64_opcode* const struct aarch64_opcode *ent = table; opcode_node **new_ent; unsigned int index = initialize_index (table); + unsigned int errors = 0; if (!ent->name) return; @@ -140,6 +141,8 @@ read_table (const struct aarch64_opcode* do { + bool match = false; + /* F_PSEUDO needs to be used together with F_ALIAS to indicate an alias opcode is a programmer friendly pseudo instruction available only in the assembly code (thus will not show up in the disassembly). */ @@ -150,12 +153,45 @@ read_table (const struct aarch64_opcode* index++; continue; } + + /* Check tied_operand against operands[]. */ + for (unsigned int i = 1; i < ARRAY_SIZE (ent->operands); ++i) + { + if (ent->operands[i] == AARCH64_OPND_NIL) + break; + + if (ent->operands[i] != ent->operands[0]) + continue; + match = true; + + if (i != ent->tied_operand) + { + fprintf (stderr, "%s: operands 1 and %u match, but tied=%u\n", + ent->name, i + 1, ent->tied_operand); + ++errors; + } + } + if (!match && ent->tied_operand + /* SME LDR/STR (array vector) tie together inner immediates only. */ + && ent->iclass != sme_ldr && ent->iclass != sme_str) + { + fprintf (stderr, "%s: no operands match, but tied=%u\n", + ent->name, ent->tied_operand); + ++errors; + } + *new_ent = new_opcode_node (); (*new_ent)->opcode = ent->opcode; (*new_ent)->mask = ent->mask; (*new_ent)->index = index++; new_ent = &((*new_ent)->next); } while ((++ent)->name); + + if (errors) + { + fprintf (stderr, "%u errors, exiting\n", errors); + xexit (3); + } } static inline void --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -6375,7 +6375,7 @@ const struct aarch64_opcode aarch64_opco SVE2p1_INSNC("fminqv",0x6417a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0), SVE2p1_INSN("dupq",0x05202400, 0xffe0fc00, sve_index1, 0, OP2 (SVE_Zd, SVE_Zn_5_INDEX), OP_SVE_VV_BHSD, 0, 0), - SVE2p1_INSN("extq",0x05602400, 0xfff0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zd, SVE_Zm_imm4), OP_SVE_BBB, 0, 0), + SVE2p1_INSN("extq",0x05602400, 0xfff0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zd, SVE_Zm_imm4), OP_SVE_BBB, 0, 1), SVE2p1_INSNC("ld1q",0xc400a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_Zt, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_SZS_QD, 0, C_SCAN_MOVPRFX, 0), SVE2p1_INSNC("ld2q",0xa490e000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt2, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0), SVE2p1_INSNC("ld3q",0xa510e000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt3, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0),