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[06/11] RISC-V: Use static xlen on ADDIW sequence

Message ID	9734125736efc8b63be17df87d38cf24bb14a156.1668487922.git.research_trasio@irq.a4lg.com
State	Accepted
Headers	Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org F2BE43889E12 To: Tsukasa OI <research_trasio@irq.a4lg.com>, Nelson Chu <nelson@rivosinc.com>, Kito Cheng <kito.cheng@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com> Cc: binutils@sourceware.org Subject: [PATCH 06/11] RISC-V: Use static xlen on ADDIW sequence Date: Tue, 15 Nov 2022 04:52:49 +0000 Message-Id: <9734125736efc8b63be17df87d38cf24bb14a156.1668487922.git.research_trasio@irq.a4lg.com> In-Reply-To: <cover.1668487922.git.research_trasio@irq.a4lg.com> References: <cover.1668487922.git.research_trasio@irq.a4lg.com> Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: list From: Tsukasa OI via Binutils <binutils@sourceware.org> Reply-To: Tsukasa OI <research_trasio@irq.a4lg.com> Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" <binutils-bounces+ouuuleilei=gmail.com@sourceware.org> X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?=
Series	RISC-V: Requirements for disassembler optimizations batch 1 \| [00/11] RISC-V: Requirements for disassembler optimizations batch 1 [01/11] opcodes/riscv-dis.c: More tidying [02/11] RISC-V: Add test for 'Zfinx' register switching [03/11] RISC-V: Make mapping symbol checking consistent [04/11] RISC-V: Split riscv_get_map_state into two steps [05/11] RISC-V: One time CSR hash table initialization [06/11] RISC-V: Use static xlen on ADDIW sequence [07/11] opcodes/riscv-dis.c: Add form feed for separation [08/11] RISC-V: Split match/print steps on disassembler [09/11] RISC-V: Reorganize disassembler state initialization [10/11] RISC-V: Reorganize arch-related initialization and management [11/11] RISC-V: Move disassembler private data initialization

Checks

Context	Check	Description
snail/binutils-gdb-check	success	Github commit url

Commit Message

Tsukasa OI Nov. 15, 2022, 4:52 a.m. UTC

  Because XLEN for the disassembler is computed and stored in the xlen
variable, this commit replaces uses of info->mach with xlen
(when testing for ADDIW / C.ADDIW address sequence).

Not just we used two ways to determine current XLEN, info->mach and xlen,
xlen is going to be more important in the future commits.

opcodes/ChangeLog:

	* riscv-dis.c (print_insn_args): Use xlen variable to determine
	whether XLEN is larger than 32.
---
 opcodes/riscv-dis.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff mbox series

Patch

diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index ec38bed747a..d4a6cdd4d4e 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -261,7 +261,7 @@  print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
 	    case 'j':
 	      if (((l & MASK_C_ADDI) == MATCH_C_ADDI) && rd != 0)
 		maybe_print_address (pd, rd, EXTRACT_CITYPE_IMM (l), 0);
-	      if (info->mach == bfd_mach_riscv64
+	      if (xlen > 32
 		  && ((l & MASK_C_ADDIW) == MATCH_C_ADDIW) && rd != 0)
 		maybe_print_address (pd, rd, EXTRACT_CITYPE_IMM (l), 1);
 	      print (info->stream, dis_style_immediate, "%d",
@@ -461,7 +461,7 @@  print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
 	  if (((l & MASK_ADDI) == MATCH_ADDI && rs1 != 0)
 	      || (l & MASK_JALR) == MATCH_JALR)
 	    maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0);
-	  if (info->mach == bfd_mach_riscv64
+	  if (xlen > 32
 	      && ((l & MASK_ADDIW) == MATCH_ADDIW) && rs1 != 0)
 	    maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 1);
 	  print (info->stream, dis_style_immediate, "%d",