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[8.43.85.97]) by mx.google.com with ESMTPS id by8-20020a0564021b0800b00523073d84c4si1489734edb.416.2023.08.02.23.01.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Aug 2023 23:01:23 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=rK4TyTzc; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8036B3858023 for ; Thu, 3 Aug 2023 06:01:20 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8036B3858023 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1691042480; bh=PrS+delOp1GcsU/kRG7eXtNVWURjbjSYNdksFsz73gQ=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=rK4TyTzcuPso+oqUQS6aROiLYpHahoy7BrkLr7OGxhOT+c8h5LFuZPxX1puiiu/XN JVIfMIBV3uYdEZcv0a0R69ZxSh+2ZN6uPgQZlx6qt/ksL5EJe0PAm4FTYk38NjYDIS 3OJ+kxQXFcHnjzsthKO7aTTQVzgiGPR+EmSFV178= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 70631385840A for ; Thu, 3 Aug 2023 06:01:04 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 70631385840A Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 5E757300089; Thu, 3 Aug 2023 06:01:02 +0000 (UTC) To: Tsukasa OI , Palmer Dabbelt , Andrew Waterman , Jim Wilson , Nelson Chu , Kito Cheng Cc: binutils@sourceware.org Subject: [PATCH] RISC-V: 'Z[fd]inx'-based 'Zve*[fd]' extensions Date: Thu, 3 Aug 2023 06:00:56 +0000 Message-ID: <8dafe6546223ecd0b97aef61009315056c5d6993.1691042441.git.research_trasio@irq.a4lg.com> Mime-Version: 1.0 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, KAM_MANYTO, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773186563305956906 X-GMAIL-MSGID: 1773186563305956906 From: Tsukasa OI In the RISC-V "V" Vector Extension specification, it states that 'Zve*f' require *either* 'F' or 'Zfinx' and 'Zve64d' requires *either* 'D' or 'Zdinx'. Current Binutils lacks support for following configurations: * 'Zve32f' and 'Zfinx' * 'Zve64f' and 'Zfinx' * 'Zve64d' and 'Zdinx' The reason behind it is probably because 'Zfinx' and 'Zdinx' are not ratified at the time when the 'V' extension support is added. Since both 'V' and 'Zfinx/Zdinx' are ratified, it's time to implement vector configurations for embedded systems as this commit does. This commit doesn't normally affect the programs that use the 'V' extension since it does not allow 'Zfinx'-based configuration. However, if the program is compiled with 'Zve*[fd]' extensions, it will need additional 'F' or 'Zfinx' extension to the "-march" option. Note that all F registers are replaced to even-numbered X registers (GPRs) in the new instruction test. bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets): Remove 2 implications 'Zve64d' -> 'D' and 'Zve32f' -> 'F'. (riscv_parse_check_conflicts): Check whether 'Zve32f' comes with either 'F' or 'Zfinx'. 'Zve64f' is indirectly checked by this. Check so that 'Zve64d' comes with either 'D' or 'Zdinx'. gas/ChangeLog: * testsuite/gas/riscv/vector-insns-fail-zve32xf.d: Explicit specify the 'F' extension to reflect incompatible changes. * testsuite/gas/riscv/march-fail-rv32i_zve32f.d: New failure test. * testsuite/gas/riscv/march-fail-rv32i_zve32f.l: Likewise. * testsuite/gas/riscv/march-fail-rv32i_zve64d.d: New failure test. * testsuite/gas/riscv/march-fail-rv32i_zve64d.l: Likewise. * testsuite/gas/riscv/vector-insns-zve64d-zdinx.s: New test, a modified subset of vector-insns.s. * testsuite/gas/riscv/vector-insns-zve64d-zdinx.d: New test, a modified subset of vector-insns.d. --- bfd/elfxx-riscv.c | 23 ++++- .../gas/riscv/march-fail-rv32i_zve32f.d | 3 + .../gas/riscv/march-fail-rv32i_zve32f.l | 2 + .../gas/riscv/march-fail-rv32i_zve64d.d | 3 + .../gas/riscv/march-fail-rv32i_zve64d.l | 3 + .../gas/riscv/vector-insns-fail-zve32xf.d | 2 +- .../gas/riscv/vector-insns-zve64d-zdinx.d | 85 ++++++++++++++++++ .../gas/riscv/vector-insns-zve64d-zdinx.s | 87 +++++++++++++++++++ 8 files changed, 205 insertions(+), 3 deletions(-) create mode 100644 gas/testsuite/gas/riscv/march-fail-rv32i_zve32f.d create mode 100644 gas/testsuite/gas/riscv/march-fail-rv32i_zve32f.l create mode 100644 gas/testsuite/gas/riscv/march-fail-rv32i_zve64d.d create mode 100644 gas/testsuite/gas/riscv/march-fail-rv32i_zve64d.l create mode 100644 gas/testsuite/gas/riscv/vector-insns-zve64d-zdinx.d create mode 100644 gas/testsuite/gas/riscv/vector-insns-zve64d-zdinx.s base-commit: 92f46037a0f672d1480f754f76a9bfa0334d099c diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 2ce95d90df52..8f61656314ca 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1110,12 +1110,10 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"v", "d", check_implicit_always}, {"v", "zve64d", check_implicit_always}, {"v", "zvl128b", check_implicit_always}, - {"zve64d", "d", check_implicit_always}, {"zve64d", "zve64f", check_implicit_always}, {"zve64f", "zve32f", check_implicit_always}, {"zve64f", "zve64x", check_implicit_always}, {"zve64f", "zvl64b", check_implicit_always}, - {"zve32f", "f", check_implicit_always}, {"zve32f", "zvl32b", check_implicit_always}, {"zve32f", "zve32x", check_implicit_always}, {"zve64x", "zve32x", check_implicit_always}, @@ -1967,6 +1965,27 @@ riscv_parse_check_conflicts (riscv_parse_subset_t *rps) no_conflict = false; } + if (riscv_lookup_subset (rps->subset_list, "zve32f", &subset) + && !riscv_lookup_subset (rps->subset_list, "v", &subset)) + { + if (riscv_lookup_subset (rps->subset_list, "zve32f", &subset) + && !riscv_lookup_subset (rps->subset_list, "f", &subset) + && !riscv_lookup_subset (rps->subset_list, "zfinx", &subset)) + { + rps->error_handler + (_("`zve32f' requires either `f/zfinx' extension")); + no_conflict = false; + } + if (riscv_lookup_subset (rps->subset_list, "zve64d", &subset) + && !riscv_lookup_subset (rps->subset_list, "d", &subset) + && !riscv_lookup_subset (rps->subset_list, "zdinx", &subset)) + { + rps->error_handler + (_("`zve64d' requires either `d/zdinx' extension")); + no_conflict = false; + } + } + bool support_zve = false; bool support_zvl = false; riscv_subset_t *s = rps->subset_list->head; diff --git a/gas/testsuite/gas/riscv/march-fail-rv32i_zve32f.d b/gas/testsuite/gas/riscv/march-fail-rv32i_zve32f.d new file mode 100644 index 000000000000..143495e8d8ad --- /dev/null +++ b/gas/testsuite/gas/riscv/march-fail-rv32i_zve32f.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_zve32f +#source: empty.s +#error_output: march-fail-rv32i_zve32f.l diff --git a/gas/testsuite/gas/riscv/march-fail-rv32i_zve32f.l b/gas/testsuite/gas/riscv/march-fail-rv32i_zve32f.l new file mode 100644 index 000000000000..d582f3bd7dfb --- /dev/null +++ b/gas/testsuite/gas/riscv/march-fail-rv32i_zve32f.l @@ -0,0 +1,2 @@ +.*Assembler messages: +.*Error: .*`zve32f' requires either `f/zfinx' extension diff --git a/gas/testsuite/gas/riscv/march-fail-rv32i_zve64d.d b/gas/testsuite/gas/riscv/march-fail-rv32i_zve64d.d new file mode 100644 index 000000000000..ecd517a22064 --- /dev/null +++ b/gas/testsuite/gas/riscv/march-fail-rv32i_zve64d.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_zve64d +#source: empty.s +#error_output: march-fail-rv32i_zve64d.l diff --git a/gas/testsuite/gas/riscv/march-fail-rv32i_zve64d.l b/gas/testsuite/gas/riscv/march-fail-rv32i_zve64d.l new file mode 100644 index 000000000000..c7b0a3ca112d --- /dev/null +++ b/gas/testsuite/gas/riscv/march-fail-rv32i_zve64d.l @@ -0,0 +1,3 @@ +.*Assembler messages: +.*Error: .*`zve32f' requires either `f/zfinx' extension +.*Error: .*`zve64d' requires either `d/zdinx' extension diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-zve32xf.d b/gas/testsuite/gas/riscv/vector-insns-fail-zve32xf.d index f3ae39b65ef2..84fc0341b232 100644 --- a/gas/testsuite/gas/riscv/vector-insns-fail-zve32xf.d +++ b/gas/testsuite/gas/riscv/vector-insns-fail-zve32xf.d @@ -1,3 +1,3 @@ -#as: -march=rv32i_zve32f +#as: -march=rv32if_zve32f #source: vector-insns.s #error_output: vector-insns-fail-zve32xf.l diff --git a/gas/testsuite/gas/riscv/vector-insns-zve64d-zdinx.d b/gas/testsuite/gas/riscv/vector-insns-zve64d-zdinx.d new file mode 100644 index 000000000000..f8361b3cc5f0 --- /dev/null +++ b/gas/testsuite/gas/riscv/vector-insns-zve64d-zdinx.d @@ -0,0 +1,85 @@ +#as: -march=rv32i_zfinx_zdinx_zve64d +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <.text>: +[ ]+[0-9a-f]+:[ ]+02865257[ ]+vfadd.vf[ ]+v4,v8,a2 +[ ]+[0-9a-f]+:[ ]+00865257[ ]+vfadd.vf[ ]+v4,v8,a2,v0.t +[ ]+[0-9a-f]+:[ ]+0a865257[ ]+vfsub.vf[ ]+v4,v8,a2 +[ ]+[0-9a-f]+:[ ]+08865257[ ]+vfsub.vf[ ]+v4,v8,a2,v0.t +[ ]+[0-9a-f]+:[ ]+9e865257[ ]+vfrsub.vf[ ]+v4,v8,a2 +[ ]+[0-9a-f]+:[ ]+9c865257[ ]+vfrsub.vf[ ]+v4,v8,a2,v0.t +[ ]+[0-9a-f]+:[ ]+c2865257[ ]+vfwadd.vf[ ]+v4,v8,a2 +[ ]+[0-9a-f]+:[ ]+c0865257[ ]+vfwadd.vf[ ]+v4,v8,a2,v0.t +[ ]+[0-9a-f]+:[ ]+ca865257[ ]+vfwsub.vf[ ]+v4,v8,a2 +[ ]+[0-9a-f]+:[ ]+c8865257[ ]+vfwsub.vf[ ]+v4,v8,a2,v0.t +[ ]+[0-9a-f]+:[ ]+d2865257[ ]+vfwadd.wf[ ]+v4,v8,a2 +[ ]+[0-9a-f]+:[ ]+d0865257[ ]+vfwadd.wf[ ]+v4,v8,a2,v0.t +[ ]+[0-9a-f]+:[ ]+da865257[ ]+vfwsub.wf[ ]+v4,v8,a2 +[ ]+[0-9a-f]+:[ ]+d8865257[ ]+vfwsub.wf[ ]+v4,v8,a2,v0.t +[ ]+[0-9a-f]+:[ ]+92865257[ ]+vfmul.vf[ ]+v4,v8,a2 +[ ]+[0-9a-f]+:[ ]+90865257[ ]+vfmul.vf[ ]+v4,v8,a2,v0.t +[ ]+[0-9a-f]+:[ ]+82865257[ ]+vfdiv.vf[ ]+v4,v8,a2 +[ ]+[0-9a-f]+:[ ]+80865257[ ]+vfdiv.vf[ ]+v4,v8,a2,v0.t +[ ]+[0-9a-f]+:[ ]+86865257[ ]+vfrdiv.vf[ ]+v4,v8,a2 +[ ]+[0-9a-f]+:[ ]+84865257[ ]+vfrdiv.vf[ ]+v4,v8,a2,v0.t +[ ]+[0-9a-f]+:[ ]+e2865257[ ]+vfwmul.vf[ ]+v4,v8,a2 +[ ]+[0-9a-f]+:[ ]+e0865257[ ]+vfwmul.vf[ ]+v4,v8,a2,v0.t +[ ]+[0-9a-f]+:[ ]+a2865257[ ]+vfmadd.vf[ ]+v4,a2,v8 +[ ]+[0-9a-f]+:[ ]+a6865257[ ]+vfnmadd.vf[ ]+v4,a2,v8 +[ ]+[0-9a-f]+:[ ]+aa865257[ ]+vfmsub.vf[ ]+v4,a2,v8 +[ ]+[0-9a-f]+:[ ]+ae865257[ ]+vfnmsub.vf[ ]+v4,a2,v8 +[ ]+[0-9a-f]+:[ ]+a0865257[ ]+vfmadd.vf[ ]+v4,a2,v8,v0.t +[ ]+[0-9a-f]+:[ ]+a4865257[ ]+vfnmadd.vf[ ]+v4,a2,v8,v0.t +[ ]+[0-9a-f]+:[ ]+a8865257[ ]+vfmsub.vf[ ]+v4,a2,v8,v0.t +[ ]+[0-9a-f]+:[ ]+ac865257[ ]+vfnmsub.vf[ ]+v4,a2,v8,v0.t +[ ]+[0-9a-f]+:[ ]+b2865257[ ]+vfmacc.vf[ ]+v4,a2,v8 +[ ]+[0-9a-f]+:[ ]+b6865257[ ]+vfnmacc.vf[ ]+v4,a2,v8 +[ ]+[0-9a-f]+:[ ]+ba865257[ ]+vfmsac.vf[ ]+v4,a2,v8 +[ ]+[0-9a-f]+:[ ]+be865257[ ]+vfnmsac.vf[ ]+v4,a2,v8 +[ ]+[0-9a-f]+:[ ]+b0865257[ ]+vfmacc.vf[ ]+v4,a2,v8,v0.t +[ ]+[0-9a-f]+:[ ]+b4865257[ ]+vfnmacc.vf[ ]+v4,a2,v8,v0.t +[ ]+[0-9a-f]+:[ ]+b8865257[ ]+vfmsac.vf[ ]+v4,a2,v8,v0.t +[ ]+[0-9a-f]+:[ ]+bc865257[ ]+vfnmsac.vf[ ]+v4,a2,v8,v0.t +[ ]+[0-9a-f]+:[ ]+f2865257[ ]+vfwmacc.vf[ ]+v4,a2,v8 +[ ]+[0-9a-f]+:[ ]+f6865257[ ]+vfwnmacc.vf[ ]+v4,a2,v8 +[ ]+[0-9a-f]+:[ ]+fa865257[ ]+vfwmsac.vf[ ]+v4,a2,v8 +[ ]+[0-9a-f]+:[ ]+fe865257[ ]+vfwnmsac.vf[ ]+v4,a2,v8 +[ ]+[0-9a-f]+:[ ]+f0865257[ ]+vfwmacc.vf[ ]+v4,a2,v8,v0.t +[ ]+[0-9a-f]+:[ ]+f4865257[ ]+vfwnmacc.vf[ ]+v4,a2,v8,v0.t +[ ]+[0-9a-f]+:[ ]+f8865257[ ]+vfwmsac.vf[ ]+v4,a2,v8,v0.t +[ ]+[0-9a-f]+:[ ]+fc865257[ ]+vfwnmsac.vf[ ]+v4,a2,v8,v0.t +[ ]+[0-9a-f]+:[ ]+12865257[ ]+vfmin.vf[ ]+v4,v8,a2 +[ ]+[0-9a-f]+:[ ]+1a865257[ ]+vfmax.vf[ ]+v4,v8,a2 +[ ]+[0-9a-f]+:[ ]+10865257[ ]+vfmin.vf[ ]+v4,v8,a2,v0.t +[ ]+[0-9a-f]+:[ ]+18865257[ ]+vfmax.vf[ ]+v4,v8,a2,v0.t +[ ]+[0-9a-f]+:[ ]+22865257[ ]+vfsgnj.vf[ ]+v4,v8,a2 +[ ]+[0-9a-f]+:[ ]+26865257[ ]+vfsgnjn.vf[ ]+v4,v8,a2 +[ ]+[0-9a-f]+:[ ]+2a865257[ ]+vfsgnjx.vf[ ]+v4,v8,a2 +[ ]+[0-9a-f]+:[ ]+20865257[ ]+vfsgnj.vf[ ]+v4,v8,a2,v0.t +[ ]+[0-9a-f]+:[ ]+24865257[ ]+vfsgnjn.vf[ ]+v4,v8,a2,v0.t +[ ]+[0-9a-f]+:[ ]+28865257[ ]+vfsgnjx.vf[ ]+v4,v8,a2,v0.t +[ ]+[0-9a-f]+:[ ]+62865257[ ]+vmfeq.vf[ ]+v4,v8,a2 +[ ]+[0-9a-f]+:[ ]+72865257[ ]+vmfne.vf[ ]+v4,v8,a2 +[ ]+[0-9a-f]+:[ ]+6e865257[ ]+vmflt.vf[ ]+v4,v8,a2 +[ ]+[0-9a-f]+:[ ]+66865257[ ]+vmfle.vf[ ]+v4,v8,a2 +[ ]+[0-9a-f]+:[ ]+76865257[ ]+vmfgt.vf[ ]+v4,v8,a2 +[ ]+[0-9a-f]+:[ ]+7e865257[ ]+vmfge.vf[ ]+v4,v8,a2 +[ ]+[0-9a-f]+:[ ]+60865257[ ]+vmfeq.vf[ ]+v4,v8,a2,v0.t +[ ]+[0-9a-f]+:[ ]+70865257[ ]+vmfne.vf[ ]+v4,v8,a2,v0.t +[ ]+[0-9a-f]+:[ ]+6c865257[ ]+vmflt.vf[ ]+v4,v8,a2,v0.t +[ ]+[0-9a-f]+:[ ]+64865257[ ]+vmfle.vf[ ]+v4,v8,a2,v0.t +[ ]+[0-9a-f]+:[ ]+74865257[ ]+vmfgt.vf[ ]+v4,v8,a2,v0.t +[ ]+[0-9a-f]+:[ ]+7c865257[ ]+vmfge.vf[ ]+v4,v8,a2,v0.t +[ ]+[0-9a-f]+:[ ]+5c865257[ ]+vfmerge.vfm[ ]+v4,v8,a2,v0 +[ ]+[0-9a-f]+:[ ]+5e065257[ ]+vfmv.v.f[ ]+v4,a2 +[ ]+[0-9a-f]+:[ ]+42801557[ ]+vfmv.f.s[ ]+a0,v8 +[ ]+[0-9a-f]+:[ ]+42065257[ ]+vfmv.s.f[ ]+v4,a2 +[ ]+[0-9a-f]+:[ ]+3a865257[ ]+vfslide1up.vf[ ]+v4,v8,a2 +[ ]+[0-9a-f]+:[ ]+3e865257[ ]+vfslide1down.vf[ ]+v4,v8,a2 +[ ]+[0-9a-f]+:[ ]+38865257[ ]+vfslide1up.vf[ ]+v4,v8,a2,v0.t +[ ]+[0-9a-f]+:[ ]+3c865257[ ]+vfslide1down.vf[ ]+v4,v8,a2,v0.t diff --git a/gas/testsuite/gas/riscv/vector-insns-zve64d-zdinx.s b/gas/testsuite/gas/riscv/vector-insns-zve64d-zdinx.s new file mode 100644 index 000000000000..99da49cfb52e --- /dev/null +++ b/gas/testsuite/gas/riscv/vector-insns-zve64d-zdinx.s @@ -0,0 +1,87 @@ + vfadd.vf v4, v8, a2 + vfadd.vf v4, v8, a2, v0.t + vfsub.vf v4, v8, a2 + vfsub.vf v4, v8, a2, v0.t + vfrsub.vf v4, v8, a2 + vfrsub.vf v4, v8, a2, v0.t + + vfwadd.vf v4, v8, a2 + vfwadd.vf v4, v8, a2, v0.t + vfwsub.vf v4, v8, a2 + vfwsub.vf v4, v8, a2, v0.t + vfwadd.wf v4, v8, a2 + vfwadd.wf v4, v8, a2, v0.t + vfwsub.wf v4, v8, a2 + vfwsub.wf v4, v8, a2, v0.t + + vfmul.vf v4, v8, a2 + vfmul.vf v4, v8, a2, v0.t + vfdiv.vf v4, v8, a2 + vfdiv.vf v4, v8, a2, v0.t + vfrdiv.vf v4, v8, a2 + vfrdiv.vf v4, v8, a2, v0.t + + vfwmul.vf v4, v8, a2 + vfwmul.vf v4, v8, a2, v0.t + + vfmadd.vf v4, a2, v8 + vfnmadd.vf v4, a2, v8 + vfmsub.vf v4, a2, v8 + vfnmsub.vf v4, a2, v8 + vfmadd.vf v4, a2, v8, v0.t + vfnmadd.vf v4, a2, v8, v0.t + vfmsub.vf v4, a2, v8, v0.t + vfnmsub.vf v4, a2, v8, v0.t + vfmacc.vf v4, a2, v8 + vfnmacc.vf v4, a2, v8 + vfmsac.vf v4, a2, v8 + vfnmsac.vf v4, a2, v8 + vfmacc.vf v4, a2, v8, v0.t + vfnmacc.vf v4, a2, v8, v0.t + vfmsac.vf v4, a2, v8, v0.t + vfnmsac.vf v4, a2, v8, v0.t + + vfwmacc.vf v4, a2, v8 + vfwnmacc.vf v4, a2, v8 + vfwmsac.vf v4, a2, v8 + vfwnmsac.vf v4, a2, v8 + vfwmacc.vf v4, a2, v8, v0.t + vfwnmacc.vf v4, a2, v8, v0.t + vfwmsac.vf v4, a2, v8, v0.t + vfwnmsac.vf v4, a2, v8, v0.t + + vfmin.vf v4, v8, a2 + vfmax.vf v4, v8, a2 + vfmin.vf v4, v8, a2, v0.t + vfmax.vf v4, v8, a2, v0.t + + vfsgnj.vf v4, v8, a2 + vfsgnjn.vf v4, v8, a2 + vfsgnjx.vf v4, v8, a2 + vfsgnj.vf v4, v8, a2, v0.t + vfsgnjn.vf v4, v8, a2, v0.t + vfsgnjx.vf v4, v8, a2, v0.t + + vmfeq.vf v4, v8, a2 + vmfne.vf v4, v8, a2 + vmflt.vf v4, v8, a2 + vmfle.vf v4, v8, a2 + vmfgt.vf v4, v8, a2 + vmfge.vf v4, v8, a2 + vmfeq.vf v4, v8, a2, v0.t + vmfne.vf v4, v8, a2, v0.t + vmflt.vf v4, v8, a2, v0.t + vmfle.vf v4, v8, a2, v0.t + vmfgt.vf v4, v8, a2, v0.t + vmfge.vf v4, v8, a2, v0.t + + vfmerge.vfm v4, v8, a2, v0 + vfmv.v.f v4, a2 + + vfmv.f.s a0, v8 + vfmv.s.f v4, a2 + + vfslide1up.vf v4, v8, a2 + vfslide1down.vf v4, v8, a2 + vfslide1up.vf v4, v8, a2, v0.t + vfslide1down.vf v4, v8, a2, v0.t