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[2/2] gdb/riscv: Fix buffer overflow on riscv_insn::fetch_instruction

Message ID 89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com
State Accepted, archived
Headers
Series RISC-V: Fix buffer overflow after long instruction support |

Checks

Context Check Description
snail/binutils-gdb-check success Github commit url

Commit Message

Tsukasa OI Oct. 4, 2022, 8:59 a.m. UTC 
  Because riscv_insn_length started to support instructions up to 176-bit,
we need to increase packet buffer size to 176-bit in size.

Note that this change will make the result of riscv_insn::fetch_instruction
partial when the instruction is longer than 64-bits.  To really support
instructions longer than 64-bit, we need something more.
---
 gdb/riscv-tdep.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Andreas Schwab Oct. 4, 2022, 9:04 a.m. UTC | #1 
On Okt 04 2022, Tsukasa OI via Gdb-patches wrote:

> diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
> index 47d8f9e601b..99307bd2de1 100644
> --- a/gdb/riscv-tdep.c
> +++ b/gdb/riscv-tdep.c
> @@ -1770,7 +1770,7 @@ riscv_insn::fetch_instruction (struct gdbarch *gdbarch,
>  			       CORE_ADDR addr, int *len)
>  {
>    enum bfd_endian byte_order = gdbarch_byte_order_for_code (gdbarch);
> -  gdb_byte buf[8];
> +  gdb_byte buf[22];

Can the magic number be derived from something else so that is adapts
automatically?
diff mbox series

Patch

diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
index 47d8f9e601b..99307bd2de1 100644
--- a/gdb/riscv-tdep.c
+++ b/gdb/riscv-tdep.c
@@ -1770,7 +1770,7 @@  riscv_insn::fetch_instruction (struct gdbarch *gdbarch,
 			       CORE_ADDR addr, int *len)
 {
   enum bfd_endian byte_order = gdbarch_byte_order_for_code (gdbarch);
-  gdb_byte buf[8];
+  gdb_byte buf[22];
   int instlen, status;
 
   /* All insns are at least 16 bits.  */