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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id d6-20020a50ea86000000b0045c3592301dsi12811520edo.191.2022.10.19.06.15.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Oct 2022 06:15:49 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=OY3yCilr; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id EF78138560A9 for ; Wed, 19 Oct 2022 13:14:06 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org EF78138560A9 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1666185247; bh=dfbPqNC0J1xT/B1AmqxmJkjUevXdqhYep3VtsqYe6dE=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=OY3yCilrmndt9IbkeegdWGlch6xyADu+QfVxtl+WDvoxL8On4sTZJklijomokBhuk dYix7THy7ljXwks8RjKzNBzTbubhDpYyY+WNUuaRjoeXceggiSIBKFEdWQp9kDj1cH 0WgTS30dQG5vUKRJcwti56Y12qWmn7eITEPj1iJ4= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 41B993858400 for ; Wed, 19 Oct 2022 13:12:50 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 41B993858400 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 939AF300089; Wed, 19 Oct 2022 13:12:48 +0000 (UTC) To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Subject: [PATCH v2 4/8] RISC-V: Remove unused instruction macros Date: Wed, 19 Oct 2022 13:11:58 +0000 Message-Id: <889d956caac0f2e95543a14afaeed97188ce384c.1666185116.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Cc: binutils@sourceware.org Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747121969336214375?= X-GMAIL-MSGID: =?utf-8?q?1747121969336214375?= This commit removes unused instruction macros. include/ChangeLog: * opcode/riscv-opc.h (MATCH_SLLI_RV32, MASK_SLLI_RV32, MATCH_SRLI_RV32, MASK_SRLI_RV32, MATCH_SRAI_RV32, MASK_SRAI_RV32, MATCH_VQMACCUVV, MASK_VQMACCUVV, MATCH_VQMACCUVX, MASK_VQMACCUVX, MATCH_VQMACCVV, MASK_VQMACCVV, MATCH_VQMACCVX, MASK_VQMACCVX, MATCH_VQMACCSUVV, MASK_VQMACCSUVV, MATCH_VQMACCSUVX, MASK_VQMACCSUVX, MATCH_VQMACCUSVX, MASK_VQMACCUSVX, MATCH_VDOTVV, MASK_VDOTVV, MATCH_VDOTUVV, MASK_VDOTUVV, MATCH_VFDOTVV, MASK_VFDOTVV): Removed as no longer used. --- include/opcode/riscv-opc.h | 29 ----------------------------- 1 file changed, 29 deletions(-) diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index e40592159cd..a30a21fe596 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -21,12 +21,6 @@ #ifndef RISCV_ENCODING_H #define RISCV_ENCODING_H /* Instruction opcode macros. */ -#define MATCH_SLLI_RV32 0x1013 -#define MASK_SLLI_RV32 0xfe00707f -#define MATCH_SRLI_RV32 0x5013 -#define MASK_SRLI_RV32 0xfe00707f -#define MATCH_SRAI_RV32 0x40005013 -#define MASK_SRAI_RV32 0xfe00707f #define MATCH_FRFLAGS 0x102073 #define MASK_FRFLAGS 0xfffff07f #define MATCH_FSFLAGS 0x101073 @@ -1657,20 +1651,6 @@ #define MASK_VWMACCSUVX 0xfc00707f #define MATCH_VWMACCUSVX 0xf8006057 #define MASK_VWMACCUSVX 0xfc00707f -#define MATCH_VQMACCUVV 0xf0000057 -#define MASK_VQMACCUVV 0xfc00707f -#define MATCH_VQMACCUVX 0xf0004057 -#define MASK_VQMACCUVX 0xfc00707f -#define MATCH_VQMACCVV 0xf4000057 -#define MASK_VQMACCVV 0xfc00707f -#define MATCH_VQMACCVX 0xf4004057 -#define MASK_VQMACCVX 0xfc00707f -#define MATCH_VQMACCSUVV 0xfc000057 -#define MASK_VQMACCSUVV 0xfc00707f -#define MATCH_VQMACCSUVX 0xfc004057 -#define MASK_VQMACCSUVX 0xfc00707f -#define MATCH_VQMACCUSVX 0xf8004057 -#define MASK_VQMACCUSVX 0xfc00707f #define MATCH_VDIVVV 0x84002057 #define MASK_VDIVVV 0xfc00707f #define MATCH_VDIVVX 0x84006057 @@ -2049,12 +2029,6 @@ #define MASK_VMV4RV 0xfe0ff07f #define MATCH_VMV8RV 0x9e03b057 #define MASK_VMV8RV 0xfe0ff07f -#define MATCH_VDOTVV 0xe4000057 -#define MASK_VDOTVV 0xfc00707f -#define MATCH_VDOTUVV 0xe0000057 -#define MASK_VDOTUVV 0xfc00707f -#define MATCH_VFDOTVV 0xe4001057 -#define MASK_VFDOTVV 0xfc00707f /* Svinval instruction. */ #define MATCH_SINVAL_VMA 0x16000073 #define MASK_SINVAL_VMA 0xfe007fff @@ -2739,9 +2713,6 @@ #define CSR_VLENB 0xc22 #endif /* RISCV_ENCODING_H */ #ifdef DECLARE_INSN -DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32) -DECLARE_INSN(srli_rv32, MATCH_SRLI_RV32, MASK_SRLI_RV32) -DECLARE_INSN(srai_rv32, MATCH_SRAI_RV32, MASK_SRAI_RV32) DECLARE_INSN(frflags, MATCH_FRFLAGS, MASK_FRFLAGS) DECLARE_INSN(fsflags, MATCH_FSFLAGS, MASK_FSFLAGS) DECLARE_INSN(fsflagsi, MATCH_FSFLAGSI, MASK_FSFLAGSI)