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x86-64: Dwarf2 register numbers for %bnd<N>

Message ID 87afbf7c-beb8-4076-9a01-8c65f92eb997@suse.com
State Accepted
Headers
Series x86-64: Dwarf2 register numbers for %bnd<N> |

Checks

Context Check Description
snail/binutils-gdb-check success Github commit url

Commit Message

Jan Beulich Jan. 12, 2024, 8:58 a.m. UTC 
  I don't see why we shouldn't record them when they have been allocated,
even if they're (bogusly) named as reserved in the ABI right now.
diff mbox series

Patch

--- a/opcodes/i386-reg.tbl
+++ b/opcodes/i386-reg.tbl
@@ -350,10 +350,10 @@  tmm5, Class=RegSIMD|Tmmword, 0, 5, Dw2In
 tmm6, Class=RegSIMD|Tmmword, 0, 6, Dw2Inval, Dw2Inval
 tmm7, Class=RegSIMD|Tmmword, 0, 7, Dw2Inval, Dw2Inval
 // Bound registers for MPX
-bnd0, Class=RegBND, 0, 0, Dw2Inval, Dw2Inval
-bnd1, Class=RegBND, 0, 1, Dw2Inval, Dw2Inval
-bnd2, Class=RegBND, 0, 2, Dw2Inval, Dw2Inval
-bnd3, Class=RegBND, 0, 3, Dw2Inval, Dw2Inval
+bnd0, Class=RegBND, 0, 0, Dw2Inval, 126
+bnd1, Class=RegBND, 0, 1, Dw2Inval, 127
+bnd2, Class=RegBND, 0, 2, Dw2Inval, 128
+bnd3, Class=RegBND, 0, 3, Dw2Inval, 129
 // No Class=Reg will make these registers rejected for all purposes except
 // for addressing.  This saves creating one extra type for RIP/EIP.
 rip, Qword, RegRex64, RegIP, Dw2Inval, 16