From patchwork Sun Nov 20 01:08:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 23366 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp928625wrr; Sat, 19 Nov 2022 17:12:53 -0800 (PST) X-Google-Smtp-Source: AA0mqf52Uj15oZg+MmrHVG8isNpyXCgGHbsuBGwPsgId40HetGkA+jjRg+qvKB1THfegbgL5Bnt+ X-Received: by 2002:a17:906:9e20:b0:7af:206:9327 with SMTP id fp32-20020a1709069e2000b007af02069327mr10990218ejc.154.1668906773799; Sat, 19 Nov 2022 17:12:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668906773; cv=none; d=google.com; s=arc-20160816; b=OgZ869fEWwIwByRlbIEgIjVYAGoRVucYvW4HJO+ie1HA2qI19XTFX/O6+QcUhUcDD0 2LshYvW+qR+USR+UMUwWB1Q9sPJNPkRLLtZ+B9dwURWxNTQWGuxAn7PQ45/xMMAm0S53 x6QtJxVgOohsFEE4kxej9GMdJC7z+wGK9hUTIll8AsTGlcmFvBUrgWBqWb8jcEvAZsNr 8RvVjHh5IdMVB0bb1/gPbWz2W958Y2fVZLdJ6O+/0kpCqyKgk72l2wNzF2f2v4JpVNVO eo5l5ap4A/vreUTGSf8hSoCQvpaXlgcudOoYUYx0ItQkFWTlMbw62Qu6Uhvj9sPow6Aj yZuw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=c9w4MxVEN+tim8nfr5DV+v5NsT0j00VJqM27kLNUwEU=; b=XGHTqL6wxJOub9oWKvxxp9mRg15LO8FgbPZCKptC5hxrKvGiYZAA7G8SGh5WpWxA2l wx+ReKG+9HXUQ5tDBX0QlbR3z91aphENJCv2AO2ZoVduKfTSA6MjYoqtcgvCtqh+F8D+ oZk1aPpFYlKl4V5UP2D34Kxs3b0Em6S9G4Jb1ZrNWhiKmACSJNNpNAWHjLUHTbp1So/t 9RcNy3Nk9Oidi2YZeQg6Z6Eu0qo+qF3vW3Uf8697Hd913/qDQagYZpVtApAy2hEUsjm1 fvdZhSv6FJtZ2c6Y0wBBj5XlijLS8SUd+S6RB3WmL8IlbU7pyjJjpCxh537zQyKHWVsr sFQg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=x1Okjrq+; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id h7-20020a0564020e0700b00468d58b2535si2043116edh.445.2022.11.19.17.12.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Nov 2022 17:12:53 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=x1Okjrq+; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5C4BE388CC12 for ; Sun, 20 Nov 2022 01:12:10 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 5C4BE388CC12 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1668906730; bh=c9w4MxVEN+tim8nfr5DV+v5NsT0j00VJqM27kLNUwEU=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=x1Okjrq+0z6reCns45Man2T/s85IAKFGs/LB6hfmfOfW3rrcz4BvE2pT9jenU2e+z oT7p3ugL7K96jbyXe0Clb/MHHJ89+hMQyuNf/5//d5kvjvivHNqZs6uDYafwMa+utM UbCLKvR0S+p8b2X5PhX/RG8H7zwMSJlZHaJmtaoI= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id C117A3889E1E for ; Sun, 20 Nov 2022 01:09:23 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org C117A3889E1E Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 2111D300089; Sun, 20 Nov 2022 01:09:22 +0000 (UTC) To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [PATCH 3/3] RISC-V: Cache instruction support Date: Sun, 20 Nov 2022 01:08:42 +0000 Message-Id: <844db363911065a3b5f0c5e4601f89ee1d7360c5.1668906514.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749975589075947301?= X-GMAIL-MSGID: =?utf-8?q?1749975589075947301?= From: Tsukasa OI Calling riscv_subset_supports repeatedly harms the performance in a measurable way (about 3-13% in total on the most cases). As a simple solution, this commit now caches instruction class support (whether specific instruction class is supported) as a signed char array. It is expected to have 5-7% performance improvements when disassembling linked RISC-V ELF programs using objdump but this is particularly effective with programs with many CSR instructions (up to ~42% on the author's PC). include/ChangeLog: * opcode/riscv.h (enum riscv_insn_class): Add NUM_INSN_CLASSES. opcodes/ChangeLog: * riscv-dis.c (riscv_insn_support_cache) New. (init_riscv_dis_state_for_arch): Clear the instruction support cache. (riscv_disassemble_insn): Cache the instruction support. --- include/opcode/riscv.h | 2 ++ opcodes/riscv-dis.c | 15 ++++++++++++++- 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index c3cbde600cb0..6a029a1034e1 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -422,6 +422,8 @@ enum riscv_insn_class INSN_CLASS_XTHEADMEMIDX, INSN_CLASS_XTHEADMEMPAIR, INSN_CLASS_XTHEADSYNC, + + NUM_INSN_CLASSES, }; /* This structure holds information for a particular instruction. */ diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 197f6a31d439..32e7b1174436 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -107,6 +107,9 @@ static bool no_aliases = false; /* If set, disassemble with numeric register names. */ static bool is_numeric = false; + +/* Instruction support cache. */ +static signed char riscv_insn_support_cache[NUM_INSN_CLASSES]; /* Set current disassembler context (dis_arch_context_current). @@ -200,6 +203,9 @@ static void init_riscv_dis_state_for_arch (void) { is_arch_changed = true; + /* Clear instruction support cache. */ + for (size_t i = 0; i < NUM_INSN_CLASSES; i++) + riscv_insn_support_cache[i] = 0; } /* Initialization (for arch and options). */ @@ -955,7 +961,14 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info) if ((op->xlen_requirement != 0) && (op->xlen_requirement != xlen)) continue; /* Is this instruction supported by the current architecture? */ - if (!riscv_multi_subset_supports (&riscv_rps_dis, op->insn_class)) + if (riscv_insn_support_cache[op->insn_class] == 0) + { + riscv_insn_support_cache[op->insn_class] + = riscv_multi_subset_supports (&riscv_rps_dis, op->insn_class) + ? +1 + : -1; + } + if (riscv_insn_support_cache[op->insn_class] < 0) continue; matched_op = op;