From patchwork Fri Nov 18 02:07:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 22058 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp734677wrr; Thu, 17 Nov 2022 18:13:57 -0800 (PST) X-Google-Smtp-Source: AA0mqf4mjlKAyPOYwIbh6oy0lmBXl2Ok8SP2ndar5bn0SOJiw9eEwSGdM2PlqhZZgbXzZrxSOTJH X-Received: by 2002:a17:906:d782:b0:78d:422b:8156 with SMTP id pj2-20020a170906d78200b0078d422b8156mr4263674ejb.589.1668737637812; Thu, 17 Nov 2022 18:13:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668737637; cv=none; d=google.com; s=arc-20160816; b=VhXKdiE7Rq1jIrl/9rcNQ8+HCos2qr0z7sRIOuYikFWMSXYLLBtvnaeFX21OVW5Pec sqVlt0mgUTxHXl4cPKA5hqoEfMg0ss5xbYhHdF4+gEYhO/LlNnPjOPSHiD67abJF3zmh 8ayqgu3EFrZ6WcAUA64ueEcNbWDaFCZ3Ips9FW3pafSRjTCRkuGdP1RtHoWoibkfh1PR b+py2DZaz6u12k2bVfXhj7vRsZMByH/pN57IMKT/2000utlBCa1vjTNlWEDq74UCLcj+ cFrwO9buN42Cg0TXslC+cPHV/jxpogy7DU6A3VDSZN0KVcT9gVUE0rvh+4XDP13p3u3U rjOA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=eVHd319/zYcERYCtnggA82FOb4EcEIycNJGmL0o7E5Q=; b=WWv2Okbq+ZBpihHzojVJedg5MNK5atey4C8OSC1i9c8tQKoXFcLQh+QI8n9073BN4L uK9PUukkYlAQiKi8NBS78SRxfdPiTIgQjbGajcW2x4VncYzOZerbfZolzpHf3BGRLBdV DQFClCoCYPPjUN59xubmf+qBhOGfAqwbGC3FSQFuZT3UKdMTcwtLehA3PqsjzlJcRwUt oAJrp0gec/7TbRq+VZu7O81PHy1RDcfWNTcVxcZ8SIsfDFm63S2yU72WiidswrpXfqp8 xsRb28ux9zwJH58AhFa1IDMHgxcO6Q3koJxecCSYEVFzyBUDZjGz242/Z4QQOxhIyK5P BLBg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=Ve4ObHkF; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id wz12-20020a170906fe4c00b0078d2a84f2f8si1639643ejb.645.2022.11.17.18.13.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Nov 2022 18:13:57 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=Ve4ObHkF; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 38DF5383F2E8 for ; Fri, 18 Nov 2022 02:11:44 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 38DF5383F2E8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1668737504; bh=eVHd319/zYcERYCtnggA82FOb4EcEIycNJGmL0o7E5Q=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=Ve4ObHkF66+4r7p23ZI05PhVjXScZyppwIimZ3cmdAhX4+gI4LG49RKQlgYs6ftC+ DA8fjkKsi0jKWE8cgJH1nebZToaHpfKZO1urWinAZe5GFo/aQZylqB269S2+Gn9Pjc 2d6eXEwnHwvQ8AMUoqOijfhhK3O5pz6VBpjAcs1I= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id DA9FC3842318 for ; Fri, 18 Nov 2022 02:09:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org DA9FC3842318 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 3E9F4300089; Fri, 18 Nov 2022 02:09:00 +0000 (UTC) To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [PATCH v4 6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w Date: Fri, 18 Nov 2022 02:07:53 +0000 Message-Id: <7f0ea4bf1af541504b72791b5217253b2450071c.1668737241.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP, UPPERCASE_50_75 autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747122234783435643?= X-GMAIL-MSGID: =?utf-8?q?1749798237266855638?= This commit renames macros for fmv.w.x and fmv.x.w instructions (formerly called fmv.s.x and fmv.x.s, respectively but renamed in the RISC-V ISA, version 2.2). include/ChangeLog: * opcode/riscv-opc.h (MATCH_FMV_X_S): Rename to MATCH_FMV_X_W. (MASK_FMV_X_S): Rename to MASK_FMV_X_W. (MATCH_FMV_S_X): Rename to MATCH_FMV_W_X. (MASK_FMV_S_X): Rename to MASK_FMV_W_X. Rename corresponding DECLARE_INSN declarations. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Use new (renamed) macros. --- include/opcode/riscv-opc.h | 12 ++++++------ opcodes/riscv-opc.c | 8 ++++---- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 05c065325f49..c7cb8a1c0bb7 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -355,8 +355,8 @@ #define MASK_FCVT_L_S 0xfff0007f #define MATCH_FCVT_LU_S 0xc0300053 #define MASK_FCVT_LU_S 0xfff0007f -#define MATCH_FMV_X_S 0xe0000053 -#define MASK_FMV_X_S 0xfff0707f +#define MATCH_FMV_X_W 0xe0000053 +#define MASK_FMV_X_W 0xfff0707f #define MATCH_FCLASS_S 0xe0001053 #define MASK_FCLASS_S 0xfff0707f #define MATCH_FCVT_W_D 0xc2000053 @@ -389,8 +389,8 @@ #define MASK_FCVT_S_L 0xfff0007f #define MATCH_FCVT_S_LU 0xd0300053 #define MASK_FCVT_S_LU 0xfff0007f -#define MATCH_FMV_S_X 0xf0000053 -#define MASK_FMV_S_X 0xfff0707f +#define MATCH_FMV_W_X 0xf0000053 +#define MASK_FMV_W_X 0xfff0707f #define MATCH_FCVT_D_W 0xd2000053 #define MASK_FCVT_D_W 0xfff0007f #define MATCH_FCVT_D_WU 0xd2100053 @@ -2885,7 +2885,7 @@ DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) -DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S) +DECLARE_INSN(fmv_x_w, MATCH_FMV_X_W, MASK_FMV_X_W) DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) @@ -2902,7 +2902,7 @@ DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) -DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X) +DECLARE_INSN(fmv_w_x, MATCH_FMV_W_X, MASK_FMV_W_X) DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 00eb57fd1252..459bf5dc5f64 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -708,10 +708,10 @@ const struct riscv_opcode riscv_opcodes[] = {"fsw", 32, INSN_CLASS_F_AND_C, "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, {"fsw", 0, INSN_CLASS_F, "T,q(s)", MATCH_FSW, MASK_FSW, match_opcode, INSN_DREF|INSN_4_BYTE }, {"fsw", 0, INSN_CLASS_F, "T,A,s", 0, (int) M_FSW, match_never, INSN_MACRO }, -{"fmv.x.w", 0, INSN_CLASS_F, "d,S", MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, 0 }, -{"fmv.w.x", 0, INSN_CLASS_F, "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 }, -{"fmv.x.s", 0, INSN_CLASS_F, "d,S", MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, 0 }, -{"fmv.s.x", 0, INSN_CLASS_F, "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 }, +{"fmv.x.w", 0, INSN_CLASS_F, "d,S", MATCH_FMV_X_W, MASK_FMV_X_W, match_opcode, 0 }, +{"fmv.w.x", 0, INSN_CLASS_F, "D,s", MATCH_FMV_W_X, MASK_FMV_W_X, match_opcode, 0 }, +{"fmv.x.s", 0, INSN_CLASS_F, "d,S", MATCH_FMV_X_W, MASK_FMV_X_W, match_opcode, 0 }, +{"fmv.s.x", 0, INSN_CLASS_F, "D,s", MATCH_FMV_W_X, MASK_FMV_W_X, match_opcode, 0 }, {"fmv.s", 0, INSN_CLASS_F_INX, "D,U", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS }, {"fneg.s", 0, INSN_CLASS_F_INX, "D,U", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_rs1_eq_rs2, INSN_ALIAS }, {"fabs.s", 0, INSN_CLASS_F_INX, "D,U", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_rs1_eq_rs2, INSN_ALIAS },