From patchwork Mon Jan 15 09:40:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinath Parvathaneni X-Patchwork-Id: 188090 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:693c:2614:b0:101:6a76:bbe3 with SMTP id mm20csp1598633dyc; Mon, 15 Jan 2024 01:42:06 -0800 (PST) X-Google-Smtp-Source: AGHT+IEBQ+ZQ8lGlgJDduSFcjO/rXW/zu0R6kl8y3bOPjMgtctk7zUb4MSMPWjXaMnzoPJkSVb3h X-Received: by 2002:ac8:5b85:0:b0:429:d709:aeb9 with SMTP id a5-20020ac85b85000000b00429d709aeb9mr4500819qta.50.1705311726582; Mon, 15 Jan 2024 01:42:06 -0800 (PST) ARC-Seal: i=4; a=rsa-sha256; t=1705311726; cv=pass; d=google.com; s=arc-20160816; b=MFAAvm92bngjZyMKkj3Su+8ZAFzQk8X4taVLcujTSmbrfBx60lDv2U52kUZkDRx+Ca O0YQrBoRtDcJ22y7b0i9QxyoFrMEJXNibjf5zmi5zTzndoGLC4eUulh33BAg0UJCLfyo Z+nt+N7Wcdnnm0dpjdts4HcjhHtquCY+NQPASBhp2jeY1Ep/X/p4re6ICrHYavb0zoi/ FDFih3eIhv7yuvuvERC6xPwh3RC97ymprqqUl/0pXdm9RRpM5HSa9CMulJYyURCgJWeT O7mmb8cZLgz/plDoUUmkpF2eXEsOY5KGdgfYL2eg2Fi0GIjfkPcUNZUSHcEEkhItaHAb m5yA== ARC-Message-Signature: i=4; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:original-authentication-results :nodisclaimer:mime-version:in-reply-to:references:cc:to:from :content-language:subject:user-agent:date:message-id :authentication-results-original:dkim-signature:dkim-signature :arc-filter:dmarc-filter:delivered-to; bh=qLrQjJaErFVQfMW4UO8nGn8l1KIHb6GJzypftoFjPtk=; fh=tMP4h4gIc+f6KYjb6V9uapAAChyUxWyPJocaPGGgdmQ=; b=yYFxN4rPhBqZcZCI+UcDtcvIulUorOYUP9DgJQKJPdzFapObvQUpxvO8XZEqdXcfQX 9xqBbSPXknhr9TG2mhflPPknFV2Jjy643wfnJxYAlj4akYBnQvfmHP/qJpys/hGeEwzs fZe89mMZp29nZGR64eNvKjcfcsnwX+yN7aaUg08UERt9kSHsQGJstlX609C2o8IrHqwU VGmSNVhw3eTXQpJVM776I87MYxn/PM7rGIofPWFDRljbrRrE1V379ECDnT2R+xVz4vOM clvqtYWa8axxlGtXWX5bsLiOQcSGxoZmNJzLpGn7L6BVXbuu4GpaCUoX9PeOYOLqpqxr Qtyw== ARC-Authentication-Results: i=4; mx.google.com; dkim=pass header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b=pgo0Nfba; dkim=pass header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b=pgo0Nfba; arc=pass (i=3); spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from server2.sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id t2-20020ac85882000000b00429c0f18707si7677614qta.574.2024.01.15.01.42.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Jan 2024 01:42:06 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b=pgo0Nfba; dkim=pass header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b=pgo0Nfba; arc=pass (i=3); spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 42DE63857B88 for ; Mon, 15 Jan 2024 09:42:06 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from EUR04-VI1-obe.outbound.protection.outlook.com (mail-vi1eur04on2048.outbound.protection.outlook.com [40.107.8.48]) by sourceware.org (Postfix) with ESMTPS id CB2D03858C42 for ; Mon, 15 Jan 2024 09:40:30 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org CB2D03858C42 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org CB2D03858C42 Authentication-Results: server2.sourceware.org; arc=pass smtp.remote-ip=40.107.8.48 ARC-Seal: i=3; a=rsa-sha256; d=sourceware.org; s=key; t=1705311633; cv=pass; b=EDxOiJrIEY/NZC/3ytpuoQoiS0ijxKeU5K2tDd6xyEYge6PYHMdTxDNzf5T/ERQSAdWSbJJQ9fQczmXTvwNVgyL3q8XSGnE2HZgBVOH8dMLFtiGLXzyigAxH/rLPr0HTlFYrcAr+SShkvRU8JGgtgTBlb4wS7WqtNndp1ijq2FA= ARC-Message-Signature: i=3; a=rsa-sha256; d=sourceware.org; s=key; t=1705311633; c=relaxed/simple; bh=qLrQjJaErFVQfMW4UO8nGn8l1KIHb6GJzypftoFjPtk=; h=DKIM-Signature:DKIM-Signature:Message-ID:Date:Subject:From:To: MIME-Version; b=EZWU1xDZbeZ3XGS3xMXJne6/0SgnXY/s7jd2OnYp6pT1xePD+C+g4EXsEtR+EW3jfyl/Af1WJD4xEb6o4Tqi5pGm55o5Ymxu1gChWShX9vPs0D9NQkCPrWli5UxgmybiryVPREifqEy83ELADStX9NbGG0R+AhxPuJ/8moo68Xs= ARC-Authentication-Results: i=3; server2.sourceware.org ARC-Seal: i=2; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=pass; b=jtjbpg5cbGAuyDBZ6bv8eMGC0deuTxKduAVdUnFW41mbDKHR40JcrxXFP9JR135hnKXsEN9FLN/E5uat1cE9lgIcowQg8gxYY0A267tSybW/Ihh/qO5trr+5FWOmLoWTNlbHT6Nl056t79a5yaRNDy6EpTEwxMqLi7sQ5Q2p1YyJvgR9KhkbelkdBvQssE3gCLXD6s3mrz1B+LfxaB6in3R2piB5zJsihP3afkaEbVh+g72Qb+ad8Wgx0vl/MYJH/LYQ5ldEJBDMpzEpfvTC6lUKA974szEGJKO5lRMIpxpg1Yc3f/mcbGRMWYpWeoniEaAtLbpdIcEMlVq/QGg3Pg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=qLrQjJaErFVQfMW4UO8nGn8l1KIHb6GJzypftoFjPtk=; b=L/O8S5dNqblA/HiFonRiG4S6AO/9BmfAlgaJ3huwYZ04ItlO637a8cJfG1kcMikXRNljGVY71v/lxaYaZ/BxOjoRV3JxqT9g8GEwOU5RWP8li2LyACHs5IMpIyUq+27Su/bV0ruIWVtSD1npa7BnKCyQ+xfo+KiGhri6fpMA4GWkcP+NjT/N9uPJh/qh2r8qvX4oq3bHdlDveL/IvF6YkNTsAbgH6NF2P1sMgwP9SW+OycOBaTd8Wy0ana4K7kQsjJ3z4yVxT6gfOTc99q80ct/YfGYIYhoNmy/rNSpV3TSu8BGszCKRCsthEWzFvANo7fE4J8Pmo+lhBdVS3siV0g== ARC-Authentication-Results: i=2; mx.microsoft.com 1; spf=pass (sender ip is 63.35.35.123) smtp.rcpttodomain=sourceware.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com; arc=pass (0 oda=1 ltdi=1 spf=[1,1,smtp.mailfrom=arm.com] dkim=[1,1,header.d=arm.com] dmarc=[1,1,header.from=arm.com]) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=qLrQjJaErFVQfMW4UO8nGn8l1KIHb6GJzypftoFjPtk=; b=pgo0Nfba+/LH1F/LvSSznF2EqUy9i6lkdpujYbJ1TD+mHyeJKtiM32UV6ip/jLM7kgEs7aYqzoMzmAEEvDld6cjyfzVgYczpNdqIefKl5Z1bHZMPHWSTYHSdr7EcfhToCRp1cNy5klf/TNSv5Gj+HXI9c3rGBp4VEZw2FltR+RA= Received: from DUZPR01CA0005.eurprd01.prod.exchangelabs.com (2603:10a6:10:3c3::9) by PAVPR08MB9628.eurprd08.prod.outlook.com (2603:10a6:102:31c::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7181.26; Mon, 15 Jan 2024 09:40:26 +0000 Received: from DB5PEPF00014B9D.eurprd02.prod.outlook.com (2603:10a6:10:3c3:cafe::9f) by DUZPR01CA0005.outlook.office365.com (2603:10a6:10:3c3::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7181.26 via Frontend Transport; Mon, 15 Jan 2024 09:40:26 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by DB5PEPF00014B9D.mail.protection.outlook.com (10.167.8.164) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7202.16 via Frontend Transport; Mon, 15 Jan 2024 09:40:26 +0000 Received: ("Tessian outbound a064b9944658:v228"); Mon, 15 Jan 2024 09:40:26 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: 19ba900b356d31c3 X-CR-MTA-TID: 64aa7808 Received: from 0719f6f214f8.2 by 64aa7808-outbound-1.mta.getcheckrecipient.com id EED0CE3F-6425-46A7-97AF-48C875F4A62D.1; Mon, 15 Jan 2024 09:40:15 +0000 Received: from EUR05-VI1-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id 0719f6f214f8.2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Mon, 15 Jan 2024 09:40:14 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=M6WjX42ez/ILd7jOMw2+u/08qAt91VQ0R4aCQKaJq+IFNNI/fDfaNhCojOexlnbgK4wjsKXTVW/PIRx/J7bTjFV+9Qon09MKgKHSqRUyI8uZ45DsEzZMRnl85DlVr+t59I03D66EkEw4Cr4udtOQklpPOan+Ku+EOhwUSup9iSrG9gdbSteE7lhJqlLPFRB+gNorF+a85PBPCtqEO856DAJYjcmvDCicO2ZY0bxjHlfWDNyvxBtEEs8q5pn09JThJiyKg8Y+2F5qa0NFcSQiUjSkleX2mI959+hWAW3hsNUMQE4MbgCrE2mzaDxo7cqphunjBz8ue7KdSV31UNfxAw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=qLrQjJaErFVQfMW4UO8nGn8l1KIHb6GJzypftoFjPtk=; b=Uph3h+4JVOjwxPk9YVDu0SZQkDDvuxttKU4c7hIP158QEtSCZQHf73r2TcP7nKkvLRCAixkWTuwyn4TdO8wHW7BzI3rbA98U42rxLnnFjrmEP6OMD1yfNiT4TX1zAoQsCBXO4jTUlm5w13BpV3pWatUlCqO4ibAZW+nrOWb9AVa7n/P7t1QPx8jdkAJxXPuGVmzrPOxNiI7RSRBVIb9FgkDIkoeMtVgbsnbZx3JFtl+66C/T1NK3oLfr5J1ZuTEr5Cnh50AS/of9qsRL/rhMhT9tHXb3+8RIUuxCIgya+v3EtFWC7kDjO0Zm2JixIMjoxY8sAHmkNA66fFmqfbXfBA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=qLrQjJaErFVQfMW4UO8nGn8l1KIHb6GJzypftoFjPtk=; b=pgo0Nfba+/LH1F/LvSSznF2EqUy9i6lkdpujYbJ1TD+mHyeJKtiM32UV6ip/jLM7kgEs7aYqzoMzmAEEvDld6cjyfzVgYczpNdqIefKl5Z1bHZMPHWSTYHSdr7EcfhToCRp1cNy5klf/TNSv5Gj+HXI9c3rGBp4VEZw2FltR+RA= Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; Received: from VE1PR08MB4893.eurprd08.prod.outlook.com (2603:10a6:802:aa::13) by AS2PR08MB9270.eurprd08.prod.outlook.com (2603:10a6:20b:59d::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7181.21; Mon, 15 Jan 2024 09:40:12 +0000 Received: from VE1PR08MB4893.eurprd08.prod.outlook.com ([fe80::bfa1:3b17:7c9a:5feb]) by VE1PR08MB4893.eurprd08.prod.outlook.com ([fe80::bfa1:3b17:7c9a:5feb%7]) with mapi id 15.20.7181.022; Mon, 15 Jan 2024 09:40:12 +0000 Message-ID: <6caee7e1-c16d-402d-9a14-e55b97244128@arm.com> Date: Mon, 15 Jan 2024 09:40:11 +0000 User-Agent: Mozilla Thunderbird Subject: [PATCH 6/6][Binutils] aarch64: Add SVE2.1 Contiguous load/store instructions. Content-Language: en-US From: Srinath Parvathaneni To: binutils@sourceware.org Cc: richard.earnshaw@arm.com, nickc@redhat.com References: <73155200-f7c2-4226-b4be-4a320ea82044@arm.com> In-Reply-To: <73155200-f7c2-4226-b4be-4a320ea82044@arm.com> X-ClientProxiedBy: LO3P265CA0002.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:bb::7) To VE1PR08MB4893.eurprd08.prod.outlook.com (2603:10a6:802:aa::13) MIME-Version: 1.0 X-MS-TrafficTypeDiagnostic: VE1PR08MB4893:EE_|AS2PR08MB9270:EE_|DB5PEPF00014B9D:EE_|PAVPR08MB9628:EE_ X-MS-Office365-Filtering-Correlation-Id: f8753b1b-12cd-4730-9e27-08dc15ae00dd X-LD-Processed: f34e5979-57d9-4aaa-ad4d-b122a662184d,ExtAddr x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: fx9Nn5yBeTL2bN84ICJBAuQpeFKnpq3beBrioavJXRjUE5aBmqiDg3JfSuq/+YxzOSvGAQ2CY5eISaaQDfis/FNZU8wC49LE5/LziGEZRlpfCbXJrcuuUvwvm45REDjZJYcPRDs9qZK66Nh+rntZdwvm08wBb3Hw1ETy7Z7zk+q/u+T/LOFhp8LcFy0fwPNS+cStS+oWnJkiS/g7JeJgcCXrb3b2uV2UYfVqWcmH5KtBWb2ghBMLhAULLe6okimSIwbiw4ptCr66hK0y+2Co9js+Q1FRnlXa2CxIpfRW9C3C8mWx3dRbz38Vyym++d/WjT8IqS638rPTgmUDfHIMgZ6q55QqV89xpDBIyRAb//DUYNuhq+DqzpNFaEDXCKQzuSi1mr+5b4kh+6+X5HnR08osuy7RoRrnHEIQe2tvodc8lGdETzK8zcvJ0c6D0J8T8B4ur4p6Cr2IO6dSqP72SJ0e1HK1Wbvj9YuONLQ5khhMHK2qvIx+7qpuUd739b6MO5NzTqPtkti2vQEKdNeuEMH3c7eMnfY4b/nhB9AjT7YrmzXMU8il1avBDNnziUWlFwYdfFhPrf0oxJxcu7tbMF0T/XsyLYZ4qerv3QhzS17T4PMfXQTvkSrUiclOBeG3LQqYT/TymawdTdKWt/LyyTrkBy0hSiDuXCAGqkxNpq45nrhi1CxXq3VwE0PaP8M9 X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:VE1PR08MB4893.eurprd08.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230031)(366004)(396003)(136003)(376002)(39860400002)(346002)(230922051799003)(186009)(64100799003)(451199024)(1800799012)(6512007)(38100700002)(86362001)(31696002)(36756003)(564344004)(6486002)(478600001)(66946007)(44832011)(6916009)(6506007)(316002)(33964004)(66476007)(66556008)(235185007)(5660300002)(2906002)(8936002)(31686004)(4326008)(8676002)(41300700001)(2616005)(26005)(45980500001)(43740500002)(357404004); DIR:OUT; SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS2PR08MB9270 Original-Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: DB5PEPF00014B9D.eurprd02.prod.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: 339a6218-2cc9-4592-3db9-08dc15adf87f X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 2GL+AlzhSQwKVYimVpNkcZNo2e1QOcGM82MpMNjSaZLIOWacn1Vm+nS9BKFxqz5X+Mf73jyCn7etcr4sv84HonNx5NidT7XH9Nm+6FzWMI5JaHK6731fHBKjJ6qqUzQcpxOQaDI+EC5PyCG7O6fFD3sRwr/nYNwkAhV43KaQ8hWVHoxe5KL+xlBhH1S6ArZVEGL95hAaXOUbAgoYRuCPQYkUp2uyAFxpdC5F6ruqQpGpH3CR/PMomuF6UVwGRKtBcT7Re1YySM/g8R8QRhiE0vSrZ+CmZuBG5dCDyS/IKOwfbzfCeP/i3006YvoRgf0Wr/wdfhYcr+s3kjkQQ3DVvXecY441v+o+Orltej/9V8J9NQbKEOQLbPSsYkRtFTctPXC5fRsfejhZuXgX3lmtN8LDd2xeWskh2UaQtjiWuP4/iPxmeLddAO+YNltiLiHxmITZiFm8xyrH0SF1/WK5JR/NRJI2Y34uUaS/xkvA8sa1YQCe/HykaiGJAuAqIs371fiiJ3ewRC0Ha1WOLvRyB+IYbCyEjSj3mx6N6323kt24neJl3sCRdwCHz6wIEznohp0OV62AAM7sFw6gedRxo33YjpEXQkOARl0DnQPl7Z5cUF7vySlcHYBjZr4XGZIUe41QB423UVBurDfBABDdyaOGtIsWKTHILz180AdYQ5ddUGHYl6UOJZhjhsZNZB4vAW55SBmW2mRtPUX8Dt4mBzJ8qA94WNwSCRHYmfAqIRjrtXIJ0VrjMYtJOiCiVl3VEPgIpJrUWY1f30CKup2Dm4b0lb47hK5DlJ9lB72zXB0oEhmrFTVJR1u5v4JjQJGq X-Forefront-Antispam-Report: CIP:63.35.35.123; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230031)(4636009)(136003)(346002)(376002)(396003)(39860400002)(230922051799003)(64100799003)(451199024)(186009)(82310400011)(1800799012)(36840700001)(46966006)(40470700004)(47076005)(6512007)(336012)(2616005)(107886003)(26005)(82740400003)(36860700001)(44832011)(4326008)(8676002)(5660300002)(235185007)(2906002)(8936002)(6486002)(478600001)(6506007)(33964004)(6916009)(316002)(70206006)(70586007)(41300700001)(356005)(81166007)(36756003)(564344004)(31696002)(86362001)(40480700001)(40460700003)(31686004)(43740500002)(357404004); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jan 2024 09:40:26.2628 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f8753b1b-12cd-4730-9e27-08dc15ae00dd X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB5PEPF00014B9D.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAVPR08MB9628 X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_LOTSOFHASH, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788148949003516519 X-GMAIL-MSGID: 1788148949003516519 Hi, This patch add support for SVE2.1 instructions ld1q, ld2q, ld3q and ld4q, st1q, st2q, st3q and st4q. Regression testing for aarch64-none-elf target and found no regressions. Ok for binutils-master? Regards, Srinath. diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 0665732fe03cc59df4ebd36ee1afbad08c22b72e..5eff6a754adea9c44432e3faacf31d20c4f6fb98 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -6749,6 +6749,9 @@ parse_operands (char *str, const aarch64_opcode *opcode) case AARCH64_OPND_SVE_ZtxN: case AARCH64_OPND_SME_Zdnx2: case AARCH64_OPND_SME_Zdnx4: + case AARCH64_OPND_SME_Zt2: + case AARCH64_OPND_SME_Zt3: + case AARCH64_OPND_SME_Zt4: case AARCH64_OPND_SME_Zmx2: case AARCH64_OPND_SME_Zmx4: case AARCH64_OPND_SME_Znx2: diff --git a/gas/testsuite/gas/aarch64/sve2p1-1-bad.l b/gas/testsuite/gas/aarch64/sve2p1-1-bad.l index 08aef46de61a6cbbe88ebac77da03ee97c9ebe7c..50a4bacc73c20324ae50b8688dd8cf5123a238ae 100644 --- a/gas/testsuite/gas/aarch64/sve2p1-1-bad.l +++ b/gas/testsuite/gas/aarch64/sve2p1-1-bad.l @@ -80,3 +80,17 @@ .*: Error: selected processor does not support `fminqv v4.2d,p3,z2.d' .*: Error: selected processor does not support `fminqv v8.2d,p4,z1.d' .*: Error: selected processor does not support `fminqv v16.4s,p7,z0.s' +.*: Error: selected processor does not support `ld1q Z0.Q,p4/Z,\[Z16.D,x0\]' +.*: Error: selected processor does not support `ld2q {Z0.Q,Z1.Q},p4/Z,\[x0,#-4,MUL VL\]' +.*: Error: selected processor does not support `ld3q {Z0.Q,Z1.Q,Z2.Q},p4/Z,\[x0,#-4,MUL VL\]' +.*: Error: selected processor does not support `ld4q {Z0.Q,Z1.Q,Z2.Q,Z3.Q},p4/Z,\[x0,#-4,MUL VL\]' +.*: Error: selected processor does not support `ld2q {Z0.Q,Z1.Q},p4/Z,\[x0,x2,lsl#4\]' +.*: Error: selected processor does not support `ld3q {Z0.Q,Z1.Q,Z2.Q},p4/Z,\[x0,x4,lsl#4\]' +.*: Error: selected processor does not support `ld4q {Z0.Q,Z1.Q,Z2.Q,Z3.Q},p4/Z,\[x0,x6,lsl#4\]' +.*: Error: selected processor does not support `st1q Z0.Q,p4,\[Z16.D,x0\]' +.*: Error: selected processor does not support `st2q {Z0.Q,Z1.Q},p4,\[x0,#-4,MUL VL\]' +.*: Error: selected processor does not support `st3q {Z0.Q,Z1.Q,Z2.Q},p4,\[x0,#-4,MUL VL\]' +.*: Error: selected processor does not support `st4q {Z0.Q,Z1.Q,Z2.Q,Z3.Q},p4,\[x0,#-4,MUL VL\]' +.*: Error: selected processor does not support `st2q {Z0.Q,Z1.Q},p4,\[x0,x2,lsl#4\]' +.*: Error: selected processor does not support `st3q {Z0.Q,Z1.Q,Z2.Q},p4,\[x0,x4,lsl#4\]' +.*: Error: selected processor does not support `st4q {Z0.Q,Z1.Q,Z2.Q,Z3.Q},p4,\[x0,x6,lsl#4\]' diff --git a/gas/testsuite/gas/aarch64/sve2p1-1.d b/gas/testsuite/gas/aarch64/sve2p1-1.d index 437ce9789834683963910141c1468ad46b273ded..daece899b38bba4daa2ca9e58dba2d551f6cf988 100644 --- a/gas/testsuite/gas/aarch64/sve2p1-1.d +++ b/gas/testsuite/gas/aarch64/sve2p1-1.d @@ -89,3 +89,17 @@ .*: 64d7ac44 fminqv v4.2d, p3, z2.d .*: 64d7b028 fminqv v8.2d, p4, z1.d .*: 6497bc10 fminqv v16.4s, p7, z0.s +.*: c400b200 ld1q z0.q, p4/z, \[z16.d, x0\] +.*: a49ef000 ld2q {z0.q, z1.q}, p4/z, \[x0, #-4, mul vl\] +.*: a51ef000 ld3q {z0.q, z1.q, z2.q}, p4/z, \[x0, #-4, mul vl\] +.*: a59ef000 ld4q {z0.q, z1.q, z2.q, z3.q}, p4/z, \[x0, #-4, mul vl\] +.*: a4a2f000 ld2h {z0.h-z1.h}, p4/z, \[x0, #4, mul vl\] +.*: a5249000 ld3q {z0.q, z1.q, z2.q}, p4/z, \[x0, x4, lsl #4\] +.*: a5a69000 ld4q {z0.q, z1.q, z2.q, z3.q}, p4/z, \[x0, x6, lsl #4\] +.*: e4203200 st1q z0.q, p4, \[z16.d, x0\] +.*: e44e1000 st2q {z0.q, z1.q}, p4, \[x0, #-4, mul vl\] +.*: e48e1000 st3q {z0.q, z1.q, z2.q}, p4, \[x0, #-4, mul vl\] +.*: e4ce1000 st4q {z0.q, z1.q, z2.q, z3.q}, p4, \[x0, #-4, mul vl\] +.*: e4621000 st2q {z0.q, z1.q}, p4, \[x0, x2, lsl #4\] +.*: e4a41000 st3q {z0.q, z1.q, z2.q}, p4, \[x0, x4, lsl #4\] +.*: e4e61000 st4q {z0.q, z1.q, z2.q, z3.q}, p4, \[x0, x6, lsl #4\] diff --git a/gas/testsuite/gas/aarch64/sve2p1-1.s b/gas/testsuite/gas/aarch64/sve2p1-1.s index b4908b2be38d927bb61a38e5aba681837d8417e1..2a1c7c107d757ae922cec5566adbace1f03e0dce 100644 --- a/gas/testsuite/gas/aarch64/sve2p1-1.s +++ b/gas/testsuite/gas/aarch64/sve2p1-1.s @@ -90,3 +90,18 @@ fminqv v2.4s, p2, z4.s fminqv v4.2d, p3, z2.d fminqv v8.2d, p4, z1.d fminqv v16.4s, p7, z0.s +ld1q Z0.Q, p4/Z, [Z16.D, x0] +ld2q {Z0.Q, Z1.Q}, p4/Z, [x0, #-4, MUL VL] +ld3q {Z0.Q, Z1.Q, Z2.Q}, p4/Z, [x0, #-4, MUL VL] +ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p4/Z, [x0, #-4, MUL VL] +ld2q {Z0.Q, Z1.Q}, p4/Z, [x0, x2, lsl #4] +ld3q {Z0.Q, Z1.Q, Z2.Q}, p4/Z, [x0, x4, lsl #4] +ld4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p4/Z, [x0, x6, lsl #4] + +st1q Z0.Q, p4, [Z16.D, x0] +st2q {Z0.Q, Z1.Q}, p4, [x0, #-4, MUL VL] +st3q {Z0.Q, Z1.Q, Z2.Q}, p4, [x0, #-4, MUL VL] +st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p4, [x0, #-4, MUL VL] +st2q {Z0.Q, Z1.Q}, p4, [x0, x2, lsl #4] +st3q {Z0.Q, Z1.Q, Z2.Q}, p4, [x0, x4, lsl #4] +st4q {Z0.Q, Z1.Q, Z2.Q, Z3.Q}, p4, [x0, x6, lsl #4] diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index de161db75d509b0ac96c604da7bc9743193d23b2..189bab5a92bcacb1ece30752817f666a34f5d81d 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -797,6 +797,9 @@ enum aarch64_opnd AARCH64_OPND_MOPS_WB_Rn, /* Rn!, in bits [5, 9]. */ AARCH64_OPND_CSSC_SIMM8, /* CSSC signed 8-bit immediate. */ AARCH64_OPND_CSSC_UIMM8, /* CSSC unsigned 8-bit immediate. */ + AARCH64_OPND_SME_Zt2, /* Qobule SVE vector register list. */ + AARCH64_OPND_SME_Zt3, /* Trible SVE vector register list. */ + AARCH64_OPND_SME_Zt4, /* Quad SVE vector register list. */ }; /* Qualifier constrains an operand. It either specifies a variant of an diff --git a/opcodes/aarch64-dis.h b/opcodes/aarch64-dis.h index 30212f2ae2c2759b5667e5a007912d22c4a702fc..48bebfea1e146e71d5fcae67c6558a35fe198e3f 100644 --- a/opcodes/aarch64-dis.h +++ b/opcodes/aarch64-dis.h @@ -139,6 +139,7 @@ AARCH64_DECL_OPD_EXTRACTOR (ext_imm_rotate2); AARCH64_DECL_OPD_EXTRACTOR (ext_x0_to_x30); AARCH64_DECL_OPD_EXTRACTOR (ext_simple_index); AARCH64_DECL_OPD_EXTRACTOR (ext_plain_shrimm); +AARCH64_DECL_OPD_EXTRACTOR (ext_sve_reglist_zt); #undef AARCH64_DECL_OPD_EXTRACTOR diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index 1381e7524402a867cee23becbaa693d1b293c28d..9e96ba35ed45a404426467b897e379ba44e7e51a 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -2160,6 +2160,21 @@ aarch64_ext_sve_reglist (const aarch64_operand *self, return true; } +/* Decode {Zn. , Zm.}. The fields array specifies which field + to use for Zn. The opcode-dependent value specifies the number + of registers in the list. */ +bool +aarch64_ext_sve_reglist_zt (const aarch64_operand *self, + aarch64_opnd_info *info, aarch64_insn code, + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) +{ + info->reglist.first_regno = extract_field (self->fields[0], code, 0); + info->reglist.num_regs = get_operand_specific_data (self); + info->reglist.stride = 1; + return true; +} + /* Decode a strided register list. The first field holds the top bit (0 or 16) and the second field holds the lower bits. The stride is 16 divided by the list length. */ diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 1d8ed26c7090e4b73489b15e74a911e33b54555c..13cd2bcd8a7a79508c340bcf618af61b622bc0fe 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -1870,6 +1870,9 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, case AARCH64_OPND_SME_Zmx4: case AARCH64_OPND_SME_Znx2: case AARCH64_OPND_SME_Znx4: + case AARCH64_OPND_SME_Zt2: + case AARCH64_OPND_SME_Zt3: + case AARCH64_OPND_SME_Zt4: num = get_operand_specific_data (&aarch64_operands[type]); if (!check_reglist (opnd, mismatch_detail, idx, num, 1)) return 0; @@ -3626,7 +3629,10 @@ print_register_list (char *buf, size_t size, const aarch64_opnd_info *opnd, /* The hyphenated form is preferred for disassembly if there are more than two registers in the list, and the register numbers are monotonically increasing in increments of one. */ - if (stride == 1 && num_regs > 1) + if (stride == 1 && num_regs > 1 + && ((opnd->type != AARCH64_OPND_SME_Zt2) + && (opnd->type != AARCH64_OPND_SME_Zt3) + && (opnd->type != AARCH64_OPND_SME_Zt4))) snprintf (buf, size, "{%s-%s}%s", style_reg (styler, "%s%d.%s", prefix, first_reg, qlf_name), style_reg (styler, "%s%d.%s", prefix, last_reg, qlf_name), tb); @@ -4071,6 +4077,9 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_SME_Znx4: case AARCH64_OPND_SME_Ztx2_STRIDED: case AARCH64_OPND_SME_Ztx4_STRIDED: + case AARCH64_OPND_SME_Zt2: + case AARCH64_OPND_SME_Zt3: + case AARCH64_OPND_SME_Zt4: print_register_list (buf, size, opnd, "z", styler); break; diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 383091ef199310b21a0741527eca50bb4a10e668..c5c5c612e508b29ab99d60e0fae20d2c8fcccde4 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -1781,6 +1781,14 @@ { \ QLF3(S_S,P_Z,S_S), \ } +#define OP_SVE_SZS_QD \ +{ \ + QLF3(S_Q,P_Z,S_D), \ +} +#define OP_SVE_SUS_QD \ +{ \ + QLF3(S_Q,NIL,S_D), \ +} #define OP_SVE_SBB \ { \ QLF3(S_S,S_B,S_B), \ @@ -6353,6 +6361,21 @@ const struct aarch64_opcode aarch64_opcode_table[] = SVE2p1_INSN("dupq",0x05202400, 0xffe0fc00, sve_index1, 0, OP2 (SVE_Zd, SVE_Zn_5_INDEX), OP_SVE_VV_BHSD, 0, 0), SVE2p1_INSN("extq",0x05602400, 0xfff0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zd, SVE_Zm_imm4), OP_SVE_BBB, 0, 0), + SVE2p1_INSNC("ld1q",0xc400a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_Zt, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_SZS_QD, 0, C_SCAN_MOVPRFX, 0), + SVE2p1_INSNC("ld2q",0xa490e000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt2, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0), + SVE2p1_INSNC("ld3q",0xa510e000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt3, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0), + SVE2p1_INSNC("ld4q",0xa590e000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt4, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0), + SVE2p1_INSNC("ld2q",0xa4a0e000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt2, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0), + SVE2p1_INSNC("ld3q",0xa5208000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt3, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0), + SVE2p1_INSNC("ld4q",0xa5a08000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt4, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0), + + SVE2p1_INSNC("st1q",0xe4202000, 0xffe0e000, sve_misc, 0, OP3 (SVE_Zt, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_SUS_QD, 0, C_SCAN_MOVPRFX, 0), + SVE2p1_INSNC("st2q",0xe4400000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt2, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0), + SVE2p1_INSNC("st3q",0xe4800000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt3, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0), + SVE2p1_INSNC("st4q",0xe4c00000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt4, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0), + SVE2p1_INSNC("st2q",0xe4600000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt2, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0), + SVE2p1_INSNC("st3q",0xe4a00000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt3, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0), + SVE2p1_INSNC("st4q",0xe4e00000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt4, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0), {0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL}, }; @@ -6989,4 +7012,13 @@ const struct aarch64_opcode aarch64_opcode_table[] = Y(IMMEDIATE, imm, "CSSC_SIMM8", OPD_F_SEXT, F(FLD_CSSC_imm8), \ "an 8-bit signed immediate") \ Y(IMMEDIATE, imm, "CSSC_UIMM8", 0, F(FLD_CSSC_imm8), \ - "an 8-bit unsigned immediate") + "an 8-bit unsigned immediate") \ + X(SVE_REGLIST, ins_sve_reglist, ext_sve_reglist_zt, "SME_Zt2", \ + 2 << OPD_F_OD_LSB, F(FLD_SVE_Zt), \ + "a list of 2 SVE vector registers") \ + X(SVE_REGLIST, ins_sve_reglist, ext_sve_reglist_zt, "SME_Zt3", \ + 3 << OPD_F_OD_LSB, F(FLD_SVE_Zt), \ + "a list of 3 SVE vector registers") \ + X(SVE_REGLIST, ins_sve_reglist, ext_sve_reglist_zt, "SME_Zt4", \ + 4 << OPD_F_OD_LSB, F(FLD_SVE_Zt), \ + "a list of 4 SVE vector registers")